Lines Matching refs:EBDMA_CSR
16 #define EBDMA_CSR 0x00UL /* Control/Status */ macro
54 writel(EBDMA_CSR_RESET, p->regs + EBDMA_CSR); in __ebus_dma_reset()
61 val = readl(p->regs + EBDMA_CSR); in __ebus_dma_reset()
76 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
77 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq()
117 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_register()
135 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
137 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
141 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
143 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq_enable()
162 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_unregister()
165 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_unregister()
185 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_request()
222 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_prepare()
246 orig_csr = csr = readl(p->regs + EBDMA_CSR); in ebus_dma_enable()
253 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_enable()