Lines Matching refs:TGT
79 #define TGT 256 macro
126 } else if (bus == TGT) { in grpci1_cfg_r32()
144 grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, tmp); in grpci1_cfg_r32()
189 } else if (bus == TGT) { in grpci1_cfg_w32()
441 grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, 0xffffffff); in grpci1_hw_init()
442 grpci1_cfg_r32(priv, TGT, 0, PCI_BASE_ADDRESS_0, &bar_sz); in grpci1_hw_init()
445 grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, pciadr); in grpci1_hw_init()
451 grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_1, ahbadr); in grpci1_hw_init()
458 grpci1_cfg_w8(priv, TGT, 0, PCI_CACHE_LINE_SIZE, 0xff); in grpci1_hw_init()
459 grpci1_cfg_w8(priv, TGT, 0, PCI_LATENCY_TIMER, 0x40); in grpci1_hw_init()
462 grpci1_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data); in grpci1_hw_init()
464 grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, data); in grpci1_hw_init()
480 grpci1_cfg_r16(priv, TGT, 0, PCI_STATUS, &status); in grpci1_err_interrupt()
505 grpci1_cfg_w16(priv, TGT, 0, PCI_STATUS, status); in grpci1_err_interrupt()