Lines Matching refs:idx
178 static u32 sparc_default_read_pmc(int idx) in sparc_default_read_pmc() argument
183 if (idx == PIC_UPPER_INDEX) in sparc_default_read_pmc()
189 static void sparc_default_write_pmc(int idx, u64 val) in sparc_default_write_pmc() argument
194 if (idx == PIC_UPPER_INDEX) in sparc_default_write_pmc()
729 static u32 sparc_vt_read_pmc(int idx) in sparc_vt_read_pmc() argument
731 u64 val = pcr_ops->read_pic(idx); in sparc_vt_read_pmc()
736 static void sparc_vt_write_pmc(int idx, u64 val) in sparc_vt_write_pmc() argument
740 pcr = pcr_ops->read_pcr(idx); in sparc_vt_write_pmc()
744 pcr_ops->write_pic(idx, val & 0xffffffff); in sparc_vt_write_pmc()
746 pcr_ops->write_pcr(idx, pcr); in sparc_vt_write_pmc()
804 static u64 event_encoding(u64 event_id, int idx) in event_encoding() argument
806 if (idx == PIC_UPPER_INDEX) in event_encoding()
813 static u64 mask_for_index(int idx) in mask_for_index() argument
815 return event_encoding(sparc_pmu->event_mask, idx); in mask_for_index()
818 static u64 nop_for_index(int idx) in nop_for_index() argument
820 return event_encoding(idx == PIC_UPPER_INDEX ? in nop_for_index()
822 sparc_pmu->lower_nop, idx); in nop_for_index()
825 … inline void sparc_pmu_enable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx) in sparc_pmu_enable_event() argument
827 u64 enc, val, mask = mask_for_index(idx); in sparc_pmu_enable_event()
831 pcr_index = idx; in sparc_pmu_enable_event()
833 enc = perf_event_get_enc(cpuc->events[idx]); in sparc_pmu_enable_event()
837 val |= event_encoding(enc, idx); in sparc_pmu_enable_event()
843 …inline void sparc_pmu_disable_event(struct cpu_hw_events *cpuc, struct hw_perf_event *hwc, int idx) in sparc_pmu_disable_event() argument
845 u64 mask = mask_for_index(idx); in sparc_pmu_disable_event()
846 u64 nop = nop_for_index(idx); in sparc_pmu_disable_event()
851 pcr_index = idx; in sparc_pmu_disable_event()
862 struct hw_perf_event *hwc, int idx) in sparc_perf_event_update() argument
870 new_raw_count = sparc_pmu->read_pmc(idx); in sparc_perf_event_update()
886 struct hw_perf_event *hwc, int idx) in sparc_perf_event_set_period() argument
910 sparc_pmu->write_pmc(idx, (u64)(-left) & 0xffffffff); in sparc_perf_event_set_period()
925 cpuc->current_idx[i] != cp->hw.idx) { in read_in_all_counters()
950 int idx = hwc->idx; in calculate_single_pcr() local
956 sparc_perf_event_set_period(cp, hwc, idx); in calculate_single_pcr()
957 cpuc->current_idx[i] = idx; in calculate_single_pcr()
960 cpuc->pcr[0] &= ~mask_for_index(idx); in calculate_single_pcr()
962 cpuc->pcr[0] |= nop_for_index(idx); in calculate_single_pcr()
964 cpuc->pcr[0] |= event_encoding(enc, idx); in calculate_single_pcr()
983 int idx = hwc->idx; in calculate_multiple_pcrs() local
988 cpuc->current_idx[i] = idx; in calculate_multiple_pcrs()
995 int idx = cp->hw.idx; in calculate_multiple_pcrs() local
997 cpuc->pcr[idx] |= cp->hw.config_base; in calculate_multiple_pcrs()
1071 int idx = active_event_index(cpuc, event); in sparc_pmu_start() local
1075 sparc_perf_event_set_period(event, &event->hw, idx); in sparc_pmu_start()
1080 sparc_pmu_enable_event(cpuc, &event->hw, idx); in sparc_pmu_start()
1086 int idx = active_event_index(cpuc, event); in sparc_pmu_stop() local
1089 sparc_pmu_disable_event(cpuc, &event->hw, idx); in sparc_pmu_stop()
1094 sparc_perf_event_update(event, &event->hw, idx); in sparc_pmu_stop()
1137 int idx = active_event_index(cpuc, event); in sparc_pmu_read() local
1140 sparc_perf_event_update(event, hwc, idx); in sparc_pmu_read()
1246 evts[i]->hw.idx = i; in sparc_check_constraints()
1293 evts[0]->hw.idx = idx0; in sparc_check_constraints()
1295 evts[1]->hw.idx = idx0 ^ 1; in sparc_check_constraints()
1475 hwc->idx = PIC_NO_INDEX; in sparc_pmu_event_init()
1617 int idx = cpuc->current_idx[i]; in perf_event_nmi_handler() local
1623 pcr_ops->write_pcr(idx, cpuc->pcr[idx]); in perf_event_nmi_handler()
1626 val = sparc_perf_event_update(event, hwc, idx); in perf_event_nmi_handler()
1631 if (!sparc_perf_event_set_period(event, hwc, idx)) in perf_event_nmi_handler()