Lines Matching refs:TILE_OP_UNSUPP
86 #define TILE_OP_UNSUPP (-1) macro
93 [PERF_COUNT_HW_CACHE_REFERENCES] = TILE_OP_UNSUPP,
94 [PERF_COUNT_HW_CACHE_MISSES] = TILE_OP_UNSUPP,
99 [PERF_COUNT_HW_BUS_CYCLES] = TILE_OP_UNSUPP,
106 [PERF_COUNT_HW_CACHE_REFERENCES] = TILE_OP_UNSUPP,
107 [PERF_COUNT_HW_CACHE_MISSES] = TILE_OP_UNSUPP,
112 [PERF_COUNT_HW_BUS_CYCLES] = TILE_OP_UNSUPP,
131 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
135 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
139 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
140 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
146 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
149 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
150 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
153 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
154 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
159 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
160 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
163 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
164 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
167 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
168 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
177 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
178 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
181 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
182 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
188 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
191 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
192 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
195 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
196 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
201 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
202 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
205 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
206 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
209 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
210 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
227 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
231 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
235 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
236 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
241 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
242 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
245 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
246 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
249 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
250 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
255 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
256 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
259 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
260 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
263 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
264 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
277 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
278 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
283 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
287 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
291 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
292 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
297 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
298 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
301 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
302 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
305 [C(RESULT_ACCESS)] = TILE_OP_UNSUPP,
306 [C(RESULT_MISS)] = TILE_OP_UNSUPP,
776 if (code == TILE_OP_UNSUPP) in tile_map_cache_event()