355 static inline u64 read_counter(int idx)  in read_counter()  argument
360 	switch (idx) {  in read_counter()
374 		WARN_ON_ONCE(idx > AUX_PERF_COUNT_1_IDX ||  in read_counter()
375 				idx < PERF_COUNT_0_IDX);  in read_counter()
384 static inline void write_counter(int idx, u64 value)  in write_counter()  argument
387 	switch (idx) {  in write_counter()
401 		WARN_ON_ONCE(idx > AUX_PERF_COUNT_1_IDX ||  in write_counter()
402 				idx < PERF_COUNT_0_IDX);  in write_counter()
414 	int shift, idx = hwc->idx;  in tile_pmu_enable_event()  local
420 	if (WARN_ON_ONCE(idx == -1))  in tile_pmu_enable_event()
423 	if (idx < tile_pmu->num_base_counters)  in tile_pmu_enable_event()
428 	switch (idx) {  in tile_pmu_enable_event()
440 		WARN_ON_ONCE(idx < PERF_COUNT_0_IDX ||  in tile_pmu_enable_event()
441 			idx > AUX_PERF_COUNT_1_IDX);  in tile_pmu_enable_event()
449 	if (idx < tile_pmu->num_base_counters)  in tile_pmu_enable_event()
463 	int idx = hwc->idx;  in tile_pmu_disable_event()  local
465 	if (idx == -1)  in tile_pmu_disable_event()
468 	if (idx < tile_pmu->num_base_counters)  in tile_pmu_disable_event()
473 	switch (idx) {  in tile_pmu_disable_event()
483 		WARN_ON_ONCE(idx < PERF_COUNT_0_IDX ||  in tile_pmu_disable_event()
484 			idx > AUX_PERF_COUNT_1_IDX);  in tile_pmu_disable_event()
491 	if (idx < tile_pmu->num_base_counters)  in tile_pmu_disable_event()
508 	int idx = hwc->idx;  in tile_perf_event_update()  local
520 	new_raw_count = read_counter(idx);  in tile_perf_event_update()
551 	int idx = hwc->idx;  in tile_event_set_period()  local
581 	write_counter(idx, (u64)(-left) & tile_pmu->cntval_mask);  in tile_event_set_period()
595 	int idx = hwc->idx;  in tile_pmu_stop()  local
597 	if (__test_and_clear_bit(idx, cpuc->active_mask)) {  in tile_pmu_stop()
599 		cpuc->events[hwc->idx] = NULL;  in tile_pmu_stop()
620 	int idx = event->hw.idx;  in tile_pmu_start()  local
625 	if (WARN_ON_ONCE(idx == -1))  in tile_pmu_start()
635 	cpuc->events[idx] = event;  in tile_pmu_start()
636 	__set_bit(idx, cpuc->active_mask);  in tile_pmu_start()
689 	event->hw.idx = b;  in tile_pmu_add()
720 			cpuc->events[event->hw.idx] = NULL;  in tile_pmu_del()
721 			__clear_bit(event->hw.idx, &cpuc->used_mask);  in tile_pmu_del()
813 	hwc->idx = -1;  in __tile_event_init()