61 struct tile_pmu {  struct
324 static const struct tile_pmu tilepmu = {
342 static const struct tile_pmu *tile_pmu __read_mostly;
423 	if (idx < tile_pmu->num_base_counters)  in tile_pmu_enable_event()
449 	if (idx < tile_pmu->num_base_counters)  in tile_pmu_enable_event()
468 	if (idx < tile_pmu->num_base_counters)  in tile_pmu_disable_event()
491 	if (idx < tile_pmu->num_base_counters)  in tile_pmu_disable_event()
505 	int shift = 64 - tile_pmu->cntval_bits;  in tile_perf_event_update()
572 	if (left > tile_pmu->max_period)  in tile_event_set_period()
573 		left = tile_pmu->max_period;  in tile_event_set_period()
581 	write_counter(idx, (u64)(-left) & tile_pmu->cntval_mask);  in tile_event_set_period()
663 	if (cpuc->n_events == tile_pmu->num_counters)  in tile_pmu_add()
676 	max_cnt = tile_pmu->num_counters;  in tile_pmu_add()
747 	if (config >= tile_pmu->max_events)  in tile_map_hw_event()
749 	return tile_pmu->hw_events[config];  in tile_map_hw_event()
760 	if (!tile_pmu->cache_events)  in tile_map_cache_event()
775 	code = (*tile_pmu->cache_events)[cache_type][cache_op][cache_result];  in tile_map_cache_event()
796 		code = tile_pmu->map_hw_event(attr->config);  in __tile_event_init()
799 		code = tile_pmu->map_cache_event(attr->config);  in __tile_event_init()
825 		hwc->sample_period = tile_pmu->max_period;  in __tile_event_init()
898 	for_each_set_bit(bit, &status, tile_pmu->num_counters) {  in tile_pmu_handle_irq()
911 		if (val & (1ULL << (tile_pmu->cntval_bits - 1)))  in tile_pmu_handle_irq()
927 	tile_pmu = &tilepmu;  in supported_pmu()