179 static void find_regs(tilegx_bundle_bits bundle, uint64_t *rd, uint64_t *ra,  in find_regs()  argument
198 		*ra = reg;  in find_regs()
205 			alias_reg_map = (1ULL << *rd) | (1ULL << *ra);  in find_regs()
209 			alias_reg_map = (1ULL << *ra) | (1ULL << *rb);  in find_regs()
249 		*ra = reg;  in find_regs()
255 			alias_reg_map = (1ULL << *rd) | (1ULL << *ra);  in find_regs()
261 			alias_reg_map = (1ULL << *ra) | (1ULL << *rb);  in find_regs()
316 static bool check_regs(uint64_t rd, uint64_t ra, uint64_t rb,  in check_regs()  argument
320 	if ((ra >= 56) && (ra != TREG_ZERO))  in check_regs()
377 static tilegx_bundle_bits  jit_x0_addi(int rd, int ra, int imm8)  in jit_x0_addi()  argument
381 		create_Dest_X0(rd) | create_SrcA_X0(ra) |  in jit_x0_addi()
386 static tilegx_bundle_bits  jit_x1_ldna(int rd, int ra)  in jit_x1_ldna()  argument
390 		create_Dest_X1(rd) | create_SrcA_X1(ra);  in jit_x1_ldna()
394 static tilegx_bundle_bits  jit_x0_dblalign(int rd, int ra, int rb)  in jit_x0_dblalign()  argument
398 		create_Dest_X0(rd) | create_SrcA_X0(ra) |  in jit_x0_dblalign()
436 static tilegx_bundle_bits  jit_x1_st1_add(int ra, int rb, int imm8)  in jit_x1_st1_add()  argument
441 		GX_INSN_X1_MASK) | create_SrcA_X1(ra) |  in jit_x1_st1_add()
446 static tilegx_bundle_bits  jit_x1_st(int ra, int rb)  in jit_x1_st()  argument
450 		create_SrcA_X1(ra) | create_SrcB_X1(rb);  in jit_x1_st()
454 static tilegx_bundle_bits  jit_x1_st_add(int ra, int rb, int imm8)  in jit_x1_st_add()  argument
459 		GX_INSN_X1_MASK) | create_SrcA_X1(ra) |  in jit_x1_st_add()
464 static tilegx_bundle_bits  jit_x1_ld(int rd, int ra)  in jit_x1_ld()  argument
468 		create_Dest_X1(rd) | create_SrcA_X1(ra);  in jit_x1_ld()
472 static tilegx_bundle_bits  jit_x1_ld_add(int rd, int ra, int imm8)  in jit_x1_ld_add()  argument
478 		create_SrcA_X1(ra) | create_Imm8_X1(imm8);  in jit_x1_ld_add()
482 static tilegx_bundle_bits  jit_x0_bfexts(int rd, int ra, int bfs, int bfe)  in jit_x0_bfexts()  argument
487 		create_Dest_X0(rd) | create_SrcA_X0(ra) |  in jit_x0_bfexts()
492 static tilegx_bundle_bits  jit_x0_bfextu(int rd, int ra, int bfs, int bfe)  in jit_x0_bfextu()  argument
497 		create_Dest_X0(rd) | create_SrcA_X0(ra) |  in jit_x0_bfextu()
502 static tilegx_bundle_bits  jit_x1_addi(int rd, int ra, int imm8)  in jit_x1_addi()  argument
506 		create_Dest_X1(rd) | create_SrcA_X1(ra) |  in jit_x1_addi()
511 static tilegx_bundle_bits  jit_x0_shrui(int rd, int ra, int imm6)  in jit_x0_shrui()  argument
516 		create_Dest_X0(rd) | create_SrcA_X0(ra) |  in jit_x0_shrui()
521 static tilegx_bundle_bits  jit_x0_rotli(int rd, int ra, int imm6)  in jit_x0_rotli()  argument
526 		create_Dest_X0(rd) | create_SrcA_X0(ra) |  in jit_x0_rotli()
531 static tilegx_bundle_bits  jit_x1_bnezt(int ra, int broff)  in jit_x1_bnezt()  argument
536 		create_SrcA_X1(ra) | create_BrOff_X1(broff);  in jit_x1_bnezt()
562 	uint64_t ra = -1, rb = -1, rd = -1, clob1 = -1, clob2 = -1, clob3 = -1;  in jit_bundle_gen()  local
643 			find_regs(bundle, 0, &ra, &rb, &clob1, &clob2,  in jit_bundle_gen()
678 			find_regs(bundle, &rd, &ra, &rb, &clob1, &clob2,  in jit_bundle_gen()
696 				find_regs(bundle, &rd, &ra, &rb, &clob1,  in jit_bundle_gen()
723 				find_regs(bundle, 0, &ra, &rb,  in jit_bundle_gen()
789 				  &ra, &rb, &clob1, &clob2, &clob3, &alias);  in jit_bundle_gen()
797 	if (check_regs(rd, ra, rb, clob1, clob2, clob3) == true)  in jit_bundle_gen()
802 		WARN_ON(!((load_store_size - 1) & (regs->regs[ra])));  in jit_bundle_gen()
900 				(unsigned char *)regs->regs[ra];  in jit_bundle_gen()
974 				current->comm, current->pid, regs->regs[ra]);  in jit_bundle_gen()
992 		if (ra < 56) {  in jit_bundle_gen()
993 			unsigned long uaa = (unsigned long)regs->regs[ra];  in jit_bundle_gen()
1018 	if ((ra != rb) && (rd != TREG_SP) && !alias &&  in jit_bundle_gen()
1033 				jit_x0_addi(ra, ra, load_store_size - 1) |  in jit_bundle_gen()
1040 					jit_x1_st1_add(ra, rb,  in jit_bundle_gen()
1044 			frag.insn[n] = jit_x1_addi(ra, ra, 1);  in jit_bundle_gen()
1046 			frag.insn[n] = jit_x1_addi(ra, ra,  in jit_bundle_gen()
1062 			if (rd == ra) {  in jit_bundle_gen()
1068 					jit_x0_addi(clob1, ra, 7) |  in jit_bundle_gen()
1071 					jit_x0_addi(clob2, ra, 0) |  in jit_bundle_gen()
1075 					jit_x1_ldna(rd, ra);  in jit_bundle_gen()
1095 					jit_x0_addi(clob1, ra, 7) |  in jit_bundle_gen()
1099 					jit_x1_ldna(rd, ra);  in jit_bundle_gen()
1108 					jit_x0_dblalign(rd, clob1, ra) |  in jit_bundle_gen()
1171 			jit_x0_addi(clob1, ra, 0)   |  in jit_bundle_gen()
1175 			jit_x0_addi(clob1, ra, load_store_size - 1)   |  in jit_bundle_gen()
1244 				jit_x0_addi(ra, ra, x1_add_imm8) |  in jit_bundle_gen()
1273 			jit_x0_addi(clob2, ra, 0) |  in jit_bundle_gen()
1314 				jit_x0_addi(ra, ra, x1_add_imm8) |  in jit_bundle_gen()
1377 				(int)alias, (int)rd, (int)ra,  in jit_bundle_gen()