Lines Matching refs:__u8
61 __u8 last_irr; /* edge detection */
62 __u8 irr; /* interrupt request register */
63 __u8 imr; /* interrupt mask register */
64 __u8 isr; /* interrupt service register */
65 __u8 priority_add; /* highest irq priority */
66 __u8 irq_base;
67 __u8 read_reg_select;
68 __u8 poll;
69 __u8 special_mask;
70 __u8 init_state;
71 __u8 auto_eoi;
72 __u8 rotate_on_auto_eoi;
73 __u8 special_fully_nested_mode;
74 __u8 init4; /* true if 4 byte init */
75 __u8 elcr; /* PIIX edge/trigger selection */
76 __u8 elcr_mask;
89 __u8 vector;
90 __u8 delivery_mode:3;
91 __u8 dest_mode:1;
92 __u8 delivery_status:1;
93 __u8 polarity:1;
94 __u8 remote_irr:1;
95 __u8 trig_mode:1;
96 __u8 mask:1;
97 __u8 reserve:7;
98 __u8 reserved[4];
99 __u8 dest_id;
129 __u8 type;
130 __u8 present, dpl, db, s, l, g, avl;
131 __u8 unusable;
132 __u8 padding;
156 __u8 fpr[8][16];
159 __u8 ftwx; /* in fxsave format */
160 __u8 pad1;
164 __u8 xmm[16][16];
232 __u8 count_latched;
233 __u8 status_latched;
234 __u8 status;
235 __u8 read_state;
236 __u8 write_state;
237 __u8 write_latch;
238 __u8 rw_mode;
239 __u8 mode;
240 __u8 bcd;
241 __u8 gate;
276 __u8 pit_reinject;
277 __u8 reserved[31];
292 __u8 injected;
293 __u8 nr;
294 __u8 has_error_code;
295 __u8 pad;
299 __u8 injected;
300 __u8 nr;
301 __u8 soft;
302 __u8 shadow;
305 __u8 injected;
306 __u8 pending;
307 __u8 masked;
308 __u8 pad;