Lines Matching refs:u64

22 	u64 _val = (val);						\
57 		u64		idxmsk64;
59 	u64	code;
60 	u64	cmask;
96 	u64	bts_buffer_base;
97 	u64	bts_index;
98 	u64	bts_absolute_maximum;
99 	u64	bts_interrupt_threshold;
100 	u64	pebs_buffer_base;
101 	u64	pebs_index;
102 	u64	pebs_absolute_maximum;
103 	u64	pebs_interrupt_threshold;
104 	u64	pebs_event_reset[MAX_PEBS_EVENTS];
112 	u64                 config;	/* extra MSR config */
113 	u64                 reg;	/* extra MSR number */
178 	u64			tags[X86_PMC_IDX_MAX];
192 	u64			pebs_enabled;
202 	u64				br_sel;
207 	u64				intel_ctrl_guest_mask;
208 	u64				intel_ctrl_host_mask;
214 	u64				intel_cp_status;
233 	u64				perf_ctr_virt_mask;
408 	u64			config_mask;
409 	u64			valid_mask;
440 		u64	lbr_format:6;
441 		u64	pebs_trap:1;
442 		u64	pebs_arch_reg:1;
443 		u64	pebs_format:4;
444 		u64	smm_freeze:1;
449 		u64	full_width_write:1;
451 	u64	capabilities;
461 		u64 event:8,
477 	u64 value;
509 	u64		(*event_map)(int);
514 	u64		cntval_mask;
521 	u64		max_period;
550 	ssize_t		(*events_sysfs_show)(char *page, u64 config);
568 	u64			intel_ctrl;
590 	u64		lbr_sel_mask;		   /* LBR_SELECT valid bits */
612 	u64 lbr_from[MAX_LBR_ENTRIES];
613 	u64 lbr_to[MAX_LBR_ENTRIES];
674 extern u64 __read_mostly hw_cache_event_ids
678 extern u64 __read_mostly hw_cache_extra_regs
683 u64 x86_perf_event_update(struct perf_event *event);
719 					  u64 enable_mask)  in __x86_pmu_enable_event()
721 	u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);  in __x86_pmu_enable_event()
780 ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
781 ssize_t intel_event_sysfs_show(char *page, u64 config);
841 void intel_pmu_enable_bts(u64 config);