Lines Matching refs:x86_pmu
1276 x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask); in __intel_pmu_enable_all()
1459 if (x86_pmu.version > 2 && hwc->config & ARCH_PERFMON_EVENTSEL_ANY) in intel_pmu_enable_fixed()
1536 if (!x86_pmu.num_counters) in intel_pmu_reset()
1543 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in intel_pmu_reset()
1547 for (idx = 0; idx < x86_pmu.num_counters_fixed; idx++) in intel_pmu_reset()
1554 if (x86_pmu.version >= 2) { in intel_pmu_reset()
1560 if (x86_pmu.lbr_nr) { in intel_pmu_reset()
1586 if (!x86_pmu.late_ack) in intel_pmu_handle_irq()
1627 x86_pmu.drain_pebs(regs); in intel_pmu_handle_irq()
1679 if (x86_pmu.late_ack) in intel_pmu_handle_irq()
1694 bts_event = x86_pmu.event_map(PERF_COUNT_HW_BRANCH_INSTRUCTIONS); in intel_bts_constraints()
1704 if (!(x86_pmu.flags & PMU_FL_HAS_RSP_1)) in intel_alt_er()
1722 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_0].event; in intel_fixup_er()
1726 event->hw.config |= x86_pmu.extra_regs[EXTRA_REG_RSP_1].event; in intel_fixup_er()
1869 if (x86_pmu.event_constraints) { in x86_get_event_constraints()
1870 for_each_event_constraint(c, x86_pmu.event_constraints) { in x86_get_event_constraints()
2300 if (event->attr.precise_ip && x86_pmu.pebs_aliases) in intel_pmu_hw_config()
2301 x86_pmu.pebs_aliases(event); in intel_pmu_hw_config()
2326 if (x86_pmu.version < 3) in intel_pmu_hw_config()
2339 if (x86_pmu.guest_get_msrs) in perf_guest_get_msrs()
2340 return x86_pmu.guest_get_msrs(nr); in perf_guest_get_msrs()
2352 arr[0].host = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_guest_mask; in intel_guest_get_msrs()
2353 arr[0].guest = x86_pmu.intel_ctrl & ~cpuc->intel_ctrl_host_mask; in intel_guest_get_msrs()
2373 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in core_guest_get_msrs()
2391 *nr = x86_pmu.num_counters; in core_guest_get_msrs()
2406 for (idx = 0; idx < x86_pmu.num_counters; idx++) { in core_pmu_enable_all()
2572 if (x86_pmu.extra_regs || x86_pmu.lbr_sel_map) { in intel_pmu_cpu_prepare()
2578 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { in intel_pmu_cpu_prepare()
2614 if (!(x86_pmu.flags & PMU_FL_NO_HT_SHARING)) { in intel_pmu_cpu_starting()
2631 if (x86_pmu.lbr_sel_map) in intel_pmu_cpu_starting()
2634 if (x86_pmu.flags & PMU_FL_EXCL_CNTRS) { in intel_pmu_cpu_starting()
2703 static __initconst const struct x86_pmu core_pmu = {
2741 static __initconst const struct x86_pmu intel_pmu = {
2797 x86_pmu.pebs = 0; in intel_clovertown_quirk()
2798 x86_pmu.pebs_constraints = NULL; in intel_clovertown_quirk()
2832 if (pebs_broken == x86_pmu.pebs_broken) in intel_snb_check_microcode()
2838 if (x86_pmu.pebs_broken) { in intel_snb_check_microcode()
2840 x86_pmu.pebs_broken = 0; in intel_snb_check_microcode()
2843 x86_pmu.pebs_broken = 1; in intel_snb_check_microcode()
2884 x86_pmu.check_microcode = intel_snb_check_microcode; in intel_sandybridge_quirk()
2903 for_each_set_bit(bit, x86_pmu.events_mask, ARRAY_SIZE(intel_arch_events_map)) { in intel_arch_events_quirk()
2914 ebx.full = x86_pmu.events_maskl; in intel_nehalem_quirk()
2924 x86_pmu.events_maskl = ebx.full; in intel_nehalem_quirk()
2943 x86_pmu.flags |= PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED; in intel_ht_bug()
2945 x86_pmu.commit_scheduling = intel_commit_scheduling; in intel_ht_bug()
2946 x86_pmu.start_scheduling = intel_start_scheduling; in intel_ht_bug()
2947 x86_pmu.stop_scheduling = intel_stop_scheduling; in intel_ht_bug()
3017 x86_pmu = core_pmu; in intel_pmu_init()
3019 x86_pmu = intel_pmu; in intel_pmu_init()
3021 x86_pmu.version = version; in intel_pmu_init()
3022 x86_pmu.num_counters = eax.split.num_counters; in intel_pmu_init()
3023 x86_pmu.cntval_bits = eax.split.bit_width; in intel_pmu_init()
3024 x86_pmu.cntval_mask = (1ULL << eax.split.bit_width) - 1; in intel_pmu_init()
3026 x86_pmu.events_maskl = ebx.full; in intel_pmu_init()
3027 x86_pmu.events_mask_len = eax.split.mask_length; in intel_pmu_init()
3029 x86_pmu.max_pebs_events = min_t(unsigned, MAX_PEBS_EVENTS, x86_pmu.num_counters); in intel_pmu_init()
3036 x86_pmu.num_counters_fixed = max((int)edx.split.num_counters_fixed, 3); in intel_pmu_init()
3042 x86_pmu.intel_cap.capabilities = capabilities; in intel_pmu_init()
3067 x86_pmu.event_constraints = intel_core2_event_constraints; in intel_pmu_init()
3068 x86_pmu.pebs_constraints = intel_core2_pebs_event_constraints; in intel_pmu_init()
3082 x86_pmu.event_constraints = intel_nehalem_event_constraints; in intel_pmu_init()
3083 x86_pmu.pebs_constraints = intel_nehalem_pebs_event_constraints; in intel_pmu_init()
3084 x86_pmu.enable_all = intel_pmu_nhm_enable_all; in intel_pmu_init()
3085 x86_pmu.extra_regs = intel_nehalem_extra_regs; in intel_pmu_init()
3087 x86_pmu.cpu_events = nhm_events_attrs; in intel_pmu_init()
3111 x86_pmu.event_constraints = intel_gen_event_constraints; in intel_pmu_init()
3112 x86_pmu.pebs_constraints = intel_atom_pebs_event_constraints; in intel_pmu_init()
3126 x86_pmu.event_constraints = intel_slm_event_constraints; in intel_pmu_init()
3127 x86_pmu.pebs_constraints = intel_slm_pebs_event_constraints; in intel_pmu_init()
3128 x86_pmu.extra_regs = intel_slm_extra_regs; in intel_pmu_init()
3129 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
3143 x86_pmu.event_constraints = intel_westmere_event_constraints; in intel_pmu_init()
3144 x86_pmu.enable_all = intel_pmu_nhm_enable_all; in intel_pmu_init()
3145 x86_pmu.pebs_constraints = intel_westmere_pebs_event_constraints; in intel_pmu_init()
3146 x86_pmu.extra_regs = intel_westmere_extra_regs; in intel_pmu_init()
3147 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
3149 x86_pmu.cpu_events = nhm_events_attrs; in intel_pmu_init()
3172 x86_pmu.event_constraints = intel_snb_event_constraints; in intel_pmu_init()
3173 x86_pmu.pebs_constraints = intel_snb_pebs_event_constraints; in intel_pmu_init()
3174 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; in intel_pmu_init()
3176 x86_pmu.extra_regs = intel_snbep_extra_regs; in intel_pmu_init()
3178 x86_pmu.extra_regs = intel_snb_extra_regs; in intel_pmu_init()
3182 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
3183 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
3185 x86_pmu.cpu_events = snb_events_attrs; in intel_pmu_init()
3210 x86_pmu.event_constraints = intel_ivb_event_constraints; in intel_pmu_init()
3211 x86_pmu.pebs_constraints = intel_ivb_pebs_event_constraints; in intel_pmu_init()
3212 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; in intel_pmu_init()
3214 x86_pmu.extra_regs = intel_snbep_extra_regs; in intel_pmu_init()
3216 x86_pmu.extra_regs = intel_snb_extra_regs; in intel_pmu_init()
3218 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
3219 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
3221 x86_pmu.cpu_events = snb_events_attrs; in intel_pmu_init()
3236 x86_pmu.late_ack = true; in intel_pmu_init()
3242 x86_pmu.event_constraints = intel_hsw_event_constraints; in intel_pmu_init()
3243 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; in intel_pmu_init()
3244 x86_pmu.extra_regs = intel_snbep_extra_regs; in intel_pmu_init()
3245 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; in intel_pmu_init()
3247 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
3248 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
3250 x86_pmu.hw_config = hsw_hw_config; in intel_pmu_init()
3251 x86_pmu.get_event_constraints = hsw_get_event_constraints; in intel_pmu_init()
3252 x86_pmu.cpu_events = hsw_events_attrs; in intel_pmu_init()
3253 x86_pmu.lbr_double_abort = true; in intel_pmu_init()
3261 x86_pmu.late_ack = true; in intel_pmu_init()
3277 x86_pmu.event_constraints = intel_bdw_event_constraints; in intel_pmu_init()
3278 x86_pmu.pebs_constraints = intel_hsw_pebs_event_constraints; in intel_pmu_init()
3279 x86_pmu.extra_regs = intel_snbep_extra_regs; in intel_pmu_init()
3280 x86_pmu.pebs_aliases = intel_pebs_aliases_snb; in intel_pmu_init()
3282 x86_pmu.flags |= PMU_FL_HAS_RSP_1; in intel_pmu_init()
3283 x86_pmu.flags |= PMU_FL_NO_HT_SHARING; in intel_pmu_init()
3285 x86_pmu.hw_config = hsw_hw_config; in intel_pmu_init()
3286 x86_pmu.get_event_constraints = hsw_get_event_constraints; in intel_pmu_init()
3287 x86_pmu.cpu_events = hsw_events_attrs; in intel_pmu_init()
3288 x86_pmu.limit_period = bdw_limit_period; in intel_pmu_init()
3293 switch (x86_pmu.version) { in intel_pmu_init()
3295 x86_pmu.event_constraints = intel_v1_event_constraints; in intel_pmu_init()
3302 x86_pmu.event_constraints = intel_gen_event_constraints; in intel_pmu_init()
3308 if (x86_pmu.num_counters > INTEL_PMC_MAX_GENERIC) { in intel_pmu_init()
3310 x86_pmu.num_counters, INTEL_PMC_MAX_GENERIC); in intel_pmu_init()
3311 x86_pmu.num_counters = INTEL_PMC_MAX_GENERIC; in intel_pmu_init()
3313 x86_pmu.intel_ctrl = (1 << x86_pmu.num_counters) - 1; in intel_pmu_init()
3315 if (x86_pmu.num_counters_fixed > INTEL_PMC_MAX_FIXED) { in intel_pmu_init()
3317 x86_pmu.num_counters_fixed, INTEL_PMC_MAX_FIXED); in intel_pmu_init()
3318 x86_pmu.num_counters_fixed = INTEL_PMC_MAX_FIXED; in intel_pmu_init()
3321 x86_pmu.intel_ctrl |= in intel_pmu_init()
3322 ((1LL << x86_pmu.num_counters_fixed)-1) << INTEL_PMC_IDX_FIXED; in intel_pmu_init()
3324 if (x86_pmu.event_constraints) { in intel_pmu_init()
3329 for_each_event_constraint(c, x86_pmu.event_constraints) { in intel_pmu_init()
3332 c->idxmsk64 |= (1ULL << x86_pmu.num_counters) - 1; in intel_pmu_init()
3335 ~(~0UL << (INTEL_PMC_IDX_FIXED + x86_pmu.num_counters_fixed)); in intel_pmu_init()
3346 if (x86_pmu.lbr_nr && !check_msr(x86_pmu.lbr_tos, 0x3UL)) in intel_pmu_init()
3347 x86_pmu.lbr_nr = 0; in intel_pmu_init()
3348 for (i = 0; i < x86_pmu.lbr_nr; i++) { in intel_pmu_init()
3349 if (!(check_msr(x86_pmu.lbr_from + i, 0xffffUL) && in intel_pmu_init()
3350 check_msr(x86_pmu.lbr_to + i, 0xffffUL))) in intel_pmu_init()
3351 x86_pmu.lbr_nr = 0; in intel_pmu_init()
3359 if (x86_pmu.extra_regs) { in intel_pmu_init()
3360 for (er = x86_pmu.extra_regs; er->msr; er++) { in intel_pmu_init()
3364 x86_pmu.lbr_sel_map = NULL; in intel_pmu_init()
3369 if (x86_pmu.intel_cap.full_width_write) { in intel_pmu_init()
3370 x86_pmu.max_period = x86_pmu.cntval_mask; in intel_pmu_init()
3371 x86_pmu.perfctr = MSR_IA32_PMC0; in intel_pmu_init()
3391 if (!(x86_pmu.flags & PMU_FL_EXCL_ENABLED)) in fixup_ht_bug()
3402 x86_pmu.flags &= ~(PMU_FL_EXCL_CNTRS | PMU_FL_EXCL_ENABLED); in fixup_ht_bug()
3404 x86_pmu.commit_scheduling = NULL; in fixup_ht_bug()
3405 x86_pmu.start_scheduling = NULL; in fixup_ht_bug()
3406 x86_pmu.stop_scheduling = NULL; in fixup_ht_bug()