256 	if (!x86_pmu.pebs)  in alloc_pebs_buffer()
293 	if (!ds || !x86_pmu.pebs)  in release_pebs_buffer()
372 	if (!x86_pmu.bts && !x86_pmu.pebs)  in release_ds_buffers()
395 	if (!x86_pmu.bts && !x86_pmu.pebs)  in reserve_ds_buffers()
401 	if (!x86_pmu.pebs)  in reserve_ds_buffers()
439 		if (x86_pmu.pebs && !pebs_err)  in reserve_ds_buffers()
830 static inline u64 intel_hsw_weight(struct pebs_record_hsw *pebs)  in intel_hsw_weight()  argument
832 	if (pebs->tsx_tuning) {  in intel_hsw_weight()
833 		union hsw_tsx_tuning tsx = { .value = pebs->tsx_tuning };  in intel_hsw_weight()
839 static inline u64 intel_hsw_transaction(struct pebs_record_hsw *pebs)  in intel_hsw_transaction()  argument
841 	u64 txn = (pebs->tsx_tuning & PEBS_HSW_TSX_FLAGS) >> 32;  in intel_hsw_transaction()
844 	if ((txn & PERF_TXN_TRANSACTION) && (pebs->ax & 1))  in intel_hsw_transaction()
845 		txn |= ((pebs->ax >> 24) & 0xff) << PERF_TXN_ABORT_SHIFT;  in intel_hsw_transaction()
861 	struct pebs_record_hsw *pebs = __pebs;  in __intel_pmu_pebs_event()  local
885 		data.weight = pebs->lat;  in __intel_pmu_pebs_event()
893 			val = load_latency_data(pebs->dse);  in __intel_pmu_pebs_event()
895 			val = precise_datala_hsw(event, pebs->dse);  in __intel_pmu_pebs_event()
897 			val = precise_store_data(pebs->dse);  in __intel_pmu_pebs_event()
912 	regs.flags = pebs->flags;  in __intel_pmu_pebs_event()
913 	set_linear_ip(&regs, pebs->ip);  in __intel_pmu_pebs_event()
914 	regs.bp = pebs->bp;  in __intel_pmu_pebs_event()
915 	regs.sp = pebs->sp;  in __intel_pmu_pebs_event()
918 		regs.ax = pebs->ax;  in __intel_pmu_pebs_event()
919 		regs.bx = pebs->bx;  in __intel_pmu_pebs_event()
920 		regs.cx = pebs->cx;  in __intel_pmu_pebs_event()
921 		regs.dx = pebs->dx;  in __intel_pmu_pebs_event()
922 		regs.si = pebs->si;  in __intel_pmu_pebs_event()
923 		regs.di = pebs->di;  in __intel_pmu_pebs_event()
924 		regs.bp = pebs->bp;  in __intel_pmu_pebs_event()
925 		regs.sp = pebs->sp;  in __intel_pmu_pebs_event()
927 		regs.flags = pebs->flags;  in __intel_pmu_pebs_event()
929 		regs.r8 = pebs->r8;  in __intel_pmu_pebs_event()
930 		regs.r9 = pebs->r9;  in __intel_pmu_pebs_event()
931 		regs.r10 = pebs->r10;  in __intel_pmu_pebs_event()
932 		regs.r11 = pebs->r11;  in __intel_pmu_pebs_event()
933 		regs.r12 = pebs->r12;  in __intel_pmu_pebs_event()
934 		regs.r13 = pebs->r13;  in __intel_pmu_pebs_event()
935 		regs.r14 = pebs->r14;  in __intel_pmu_pebs_event()
936 		regs.r15 = pebs->r15;  in __intel_pmu_pebs_event()
941 		regs.ip = pebs->real_ip;  in __intel_pmu_pebs_event()
950 		data.addr = pebs->dla;  in __intel_pmu_pebs_event()
955 			data.weight = intel_hsw_weight(pebs);  in __intel_pmu_pebs_event()
958 			data.txn = intel_hsw_transaction(pebs);  in __intel_pmu_pebs_event()
1077 	x86_pmu.pebs = boot_cpu_has(X86_FEATURE_PEBS);  in intel_ds_init()
1078 	if (x86_pmu.pebs) {  in intel_ds_init()
1103 			x86_pmu.pebs = 0;  in intel_ds_init()
1112 	if (!x86_pmu.bts && !x86_pmu.pebs)  in perf_restore_debug_store()