107 static inline u64 op_amd_randomize_ibs_op(u64 val)  in op_amd_randomize_ibs_op()  argument
125 		val += (s8)(random >> 4);  in op_amd_randomize_ibs_op()
127 		val |= (u64)(random & IBS_RANDOM_MASK) << 32;  in op_amd_randomize_ibs_op()
129 	return val;  in op_amd_randomize_ibs_op()
136 	u64 val, ctl;  in op_amd_handle_ibs()  local
145 			rdmsrl(MSR_AMD64_IBSFETCHLINAD, val);  in op_amd_handle_ibs()
146 			oprofile_write_reserve(&entry, regs, val,  in op_amd_handle_ibs()
148 			oprofile_add_data64(&entry, val);  in op_amd_handle_ibs()
150 			rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val);  in op_amd_handle_ibs()
151 			oprofile_add_data64(&entry, val);  in op_amd_handle_ibs()
164 			rdmsrl(MSR_AMD64_IBSOPRIP, val);  in op_amd_handle_ibs()
165 			oprofile_write_reserve(&entry, regs, val, IBS_OP_CODE,  in op_amd_handle_ibs()
167 			oprofile_add_data64(&entry, val);  in op_amd_handle_ibs()
168 			rdmsrl(MSR_AMD64_IBSOPDATA, val);  in op_amd_handle_ibs()
169 			oprofile_add_data64(&entry, val);  in op_amd_handle_ibs()
170 			rdmsrl(MSR_AMD64_IBSOPDATA2, val);  in op_amd_handle_ibs()
171 			oprofile_add_data64(&entry, val);  in op_amd_handle_ibs()
172 			rdmsrl(MSR_AMD64_IBSOPDATA3, val);  in op_amd_handle_ibs()
173 			oprofile_add_data64(&entry, val);  in op_amd_handle_ibs()
174 			rdmsrl(MSR_AMD64_IBSDCLINAD, val);  in op_amd_handle_ibs()
175 			oprofile_add_data64(&entry, val);  in op_amd_handle_ibs()
176 			rdmsrl(MSR_AMD64_IBSDCPHYSAD, val);  in op_amd_handle_ibs()
177 			oprofile_add_data64(&entry, val);  in op_amd_handle_ibs()
179 				rdmsrl(MSR_AMD64_IBSBRTARGET, val);  in op_amd_handle_ibs()
180 				oprofile_add_data(&entry, (unsigned long)val);  in op_amd_handle_ibs()
193 	u64 val;  in op_amd_start_ibs()  local
207 		val = ibs_config.max_cnt_fetch >> 4;  in op_amd_start_ibs()
208 		val = min(val, IBS_FETCH_MAX_CNT);  in op_amd_start_ibs()
209 		ibs_config.max_cnt_fetch = val << 4;  in op_amd_start_ibs()
210 		val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0;  in op_amd_start_ibs()
211 		val |= IBS_FETCH_ENABLE;  in op_amd_start_ibs()
212 		wrmsrl(MSR_AMD64_IBSFETCHCTL, val);  in op_amd_start_ibs()
216 		val = ibs_config.max_cnt_op >> 4;  in op_amd_start_ibs()
222 			val = clamp(val, 0x0081ULL, 0xFF80ULL);  in op_amd_start_ibs()
223 			ibs_config.max_cnt_op = val << 4;  in op_amd_start_ibs()
231 			val += IBS_RANDOM_MAXCNT_OFFSET;  in op_amd_start_ibs()
233 				val = min(val, IBS_OP_MAX_CNT_EXT);  in op_amd_start_ibs()
235 				val = min(val, IBS_OP_MAX_CNT);  in op_amd_start_ibs()
237 				(val - IBS_RANDOM_MAXCNT_OFFSET) << 4;  in op_amd_start_ibs()
239 		val = ((val & ~IBS_OP_MAX_CNT) << 4) | (val & IBS_OP_MAX_CNT);  in op_amd_start_ibs()
240 		val |= ibs_config.dispatched_ops ? IBS_OP_CNT_CTL : 0;  in op_amd_start_ibs()
241 		val |= IBS_OP_ENABLE;  in op_amd_start_ibs()
242 		ibs_state.ibs_op_ctl = val;  in op_amd_start_ibs()
248 		val = op_amd_randomize_ibs_op(ibs_state.ibs_op_ctl);  in op_amd_start_ibs()
249 		wrmsrl(MSR_AMD64_IBSOPCTL, val);  in op_amd_start_ibs()
272 	u64 val;  in op_mux_switch_ctrl()  local
280 		rdmsrl(msrs->controls[i].addr, val);  in op_mux_switch_ctrl()
281 		val &= model->reserved;  in op_mux_switch_ctrl()
282 		val |= op_x86_get_ctrl(model, &counter_config[virt]);  in op_mux_switch_ctrl()
283 		wrmsrl(msrs->controls[i].addr, val);  in op_mux_switch_ctrl()
337 	u64 val;  in op_amd_setup_ctrs()  local
353 		rdmsrl(msrs->controls[i].addr, val);  in op_amd_setup_ctrs()
354 		if (val & ARCH_PERFMON_EVENTSEL_ENABLE)  in op_amd_setup_ctrs()
356 		val &= model->reserved;  in op_amd_setup_ctrs()
357 		wrmsrl(msrs->controls[i].addr, val);  in op_amd_setup_ctrs()
375 		rdmsrl(msrs->controls[i].addr, val);  in op_amd_setup_ctrs()
376 		val &= model->reserved;  in op_amd_setup_ctrs()
377 		val |= op_x86_get_ctrl(model, &counter_config[virt]);  in op_amd_setup_ctrs()
378 		wrmsrl(msrs->controls[i].addr, val);  in op_amd_setup_ctrs()
385 	u64 val;  in op_amd_check_ctrs()  local
392 		rdmsrl(msrs->counters[i].addr, val);  in op_amd_check_ctrs()
394 		if (val & OP_CTR_OVERFLOW)  in op_amd_check_ctrs()
408 	u64 val;  in op_amd_start()  local
414 		rdmsrl(msrs->controls[i].addr, val);  in op_amd_start()
415 		val |= ARCH_PERFMON_EVENTSEL_ENABLE;  in op_amd_start()
416 		wrmsrl(msrs->controls[i].addr, val);  in op_amd_start()
424 	u64 val;  in op_amd_stop()  local
434 		rdmsrl(msrs->controls[i].addr, val);  in op_amd_stop()
435 		val &= ~ARCH_PERFMON_EVENTSEL_ENABLE;  in op_amd_stop()
436 		wrmsrl(msrs->controls[i].addr, val);  in op_amd_stop()