39 #define SCFG_OFFSET					0x1000  macro
197 	writel(BIT(0), tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);  in tegra_ahci_controller_init()
200 		SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);  in tegra_ahci_controller_init()
207 	writel(val, tegra->sata_regs + SCFG_OFFSET +  in tegra_ahci_controller_init()
211 			SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);  in tegra_ahci_controller_init()
218 	writel(val, tegra->sata_regs + SCFG_OFFSET +  in tegra_ahci_controller_init()
222 		tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11);  in tegra_ahci_controller_init()
224 		tegra->sata_regs + SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2);  in tegra_ahci_controller_init()
226 	writel(0, tegra->sata_regs + SCFG_OFFSET + T_SATA0_INDEX);  in tegra_ahci_controller_init()
230 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
232 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
234 	writel(0x01060100, tegra->sata_regs + SCFG_OFFSET + T_SATA0_BKDOOR_CC);  in tegra_ahci_controller_init()
236 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
238 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_SATA);  in tegra_ahci_controller_init()
242 	val = readl(tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);  in tegra_ahci_controller_init()
245 	writel(val, tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_1);  in tegra_ahci_controller_init()
253 	       tegra->sata_regs + SCFG_OFFSET + T_SATA0_CFG_9);  in tegra_ahci_controller_init()