267 	writel(HOST_RESET, dd->mmio + HOST_CTL);  in mtip_hba_reset()
270 	readl(dd->mmio + HOST_CTL);  in mtip_hba_reset()
279 	} while ((readl(dd->mmio + HOST_CTL) & HOST_RESET)  in mtip_hba_reset()
282 	if (readl(dd->mmio + HOST_CTL) & HOST_RESET)  in mtip_hba_reset()
327 	tmp = readl(port->mmio + PORT_CMD);  in mtip_enable_fis()
329 		writel(tmp | PORT_CMD_FIS_RX, port->mmio + PORT_CMD);  in mtip_enable_fis()
331 		writel(tmp & ~PORT_CMD_FIS_RX, port->mmio + PORT_CMD);  in mtip_enable_fis()
334 	readl(port->mmio + PORT_CMD);  in mtip_enable_fis()
353 	tmp = readl(port->mmio + PORT_CMD);  in mtip_enable_engine()
355 		writel(tmp | PORT_CMD_START, port->mmio + PORT_CMD);  in mtip_enable_engine()
357 		writel(tmp & ~PORT_CMD_START, port->mmio + PORT_CMD);  in mtip_enable_engine()
359 	readl(port->mmio + PORT_CMD);  in mtip_enable_engine()
390 	writel(0, port->mmio + PORT_IRQ_MASK);  in mtip_deinit_port()
418 	if (readl(port->dd->mmio + HOST_CAP) & HOST_CAP_64) {  in mtip_init_port()
420 			 port->mmio + PORT_LST_ADDR_HI);  in mtip_init_port()
422 			 port->mmio + PORT_FIS_ADDR_HI);  in mtip_init_port()
426 			port->mmio + PORT_LST_ADDR);  in mtip_init_port()
427 	writel(port->rxfis_dma & 0xFFFFFFFF, port->mmio + PORT_FIS_ADDR);  in mtip_init_port()
430 	writel(readl(port->mmio + PORT_SCR_ERR), port->mmio + PORT_SCR_ERR);  in mtip_init_port()
437 	writel(readl(port->mmio + PORT_IRQ_STAT), port->mmio + PORT_IRQ_STAT);  in mtip_init_port()
440 	writel(readl(port->dd->mmio + HOST_IRQ_STAT),  in mtip_init_port()
441 					port->dd->mmio + HOST_IRQ_STAT);  in mtip_init_port()
444 	writel(DEF_PORT_IRQ, port->mmio + PORT_IRQ_MASK);  in mtip_init_port()
464 	while ((readl(port->mmio + PORT_CMD) & PORT_CMD_LIST_ON)  in mtip_restart_port()
475 	if (readl(port->mmio + PORT_CMD) & PORT_CMD_LIST_ON) {  in mtip_restart_port()
490 	writel(readl(port->mmio + PORT_SCR_CTL) |  in mtip_restart_port()
491 			 1, port->mmio + PORT_SCR_CTL);  in mtip_restart_port()
492 	readl(port->mmio + PORT_SCR_CTL);  in mtip_restart_port()
503 	writel(readl(port->mmio + PORT_SCR_CTL) & ~1,  in mtip_restart_port()
504 			 port->mmio + PORT_SCR_CTL);  in mtip_restart_port()
505 	readl(port->mmio + PORT_SCR_CTL);  in mtip_restart_port()
509 	while (((readl(port->mmio + PORT_SCR_STAT) & 0x01) == 0)  in mtip_restart_port()
516 	if ((readl(port->mmio + PORT_SCR_STAT) & 0x01) == 0)  in mtip_restart_port()
540 	writel(readl(dd->mmio + HOST_CTL) | HOST_IRQ_EN,  in mtip_device_reset()
541 					dd->mmio + HOST_CTL);  in mtip_device_reset()
830 		writel(0xffffffff, dd->mmio + HOST_IRQ_STAT);  in mtip_workq_sdbfx()
862 		writel((1 << 26), dd->port->mmio + PORT_SCR_ERR);  in mtip_process_errors()
868 		writel((1 << 16), dd->port->mmio + PORT_SCR_ERR);  in mtip_process_errors()
893 	hba_stat = readl(dd->mmio + HOST_IRQ_STAT);  in mtip_handle_irq()
898 		port_stat = readl(port->mmio + PORT_IRQ_STAT);  in mtip_handle_irq()
903 		writel(port_stat, port->mmio + PORT_IRQ_STAT);  in mtip_handle_irq()
961 		writel(hba_stat, dd->mmio + HOST_IRQ_STAT);  in mtip_handle_irq()
996 	task_file_data = readl(port->mmio+PORT_TFDATA);  in mtip_pause_ncq()
1228 			port_stat = readl(port->mmio + PORT_IRQ_STAT);  in mtip_exec_internal_command()
1240 				writel(port_stat, port->mmio + PORT_IRQ_STAT);  in mtip_exec_internal_command()
1241 				hba_stat = readl(dd->mmio + HOST_IRQ_STAT);  in mtip_exec_internal_command()
1244 						dd->mmio + HOST_IRQ_STAT);  in mtip_exec_internal_command()
2183 	task_file_data = readl(dd->port->mmio+PORT_TFDATA);  in exec_drive_taskfile()
2630 				readl(dd->port->mmio + PORT_IRQ_STAT));  in mtip_hw_read_registers()
2632 				readl(dd->mmio + HOST_IRQ_STAT));  in mtip_hw_read_registers()
2801 	hwdata = readl(dd->mmio + HOST_HSORG);  in hba_setup()
2807 		dd->mmio + HOST_HSORG);  in hba_setup()
2837 	hwdata = readl(dd->mmio + HOST_HSORG);  in mtip_detect_product()
3165 	dd->mmio = pcim_iomap_table(dd->pdev)[MTIP_ABAR];  in mtip_hw_init()
3201 	dd->port->mmio	= dd->mmio + PORT_OFFSET;  in mtip_hw_init()
3212 			dd->port->mmio + i*0x80 + PORT_SCR_ACT;  in mtip_hw_init()
3214 			dd->port->mmio + i*0x80 + PORT_COMMAND_ISSUE;  in mtip_hw_init()
3216 			dd->port->mmio + i*0x80 + PORT_SDBV;  in mtip_hw_init()
3221 	while (((readl(dd->port->mmio + PORT_SCR_STAT) & 0x0F) != 0x03) &&  in mtip_hw_init()
3243 	if (!(readl(dd->mmio + HOST_CAP) & HOST_CAP_NZDMA)) {  in mtip_hw_init()
3252 		writel(readl(dd->mmio + HOST_IRQ_STAT),  in mtip_hw_init()
3253 			dd->mmio + HOST_IRQ_STAT);  in mtip_hw_init()
3275 	writel(readl(dd->mmio + HOST_CTL) | HOST_IRQ_EN,  in mtip_hw_init()
3276 					dd->mmio + HOST_CTL);  in mtip_hw_init()
3289 	writel(readl(dd->mmio + HOST_CTL) & ~HOST_IRQ_EN,  in mtip_hw_init()
3290 			dd->mmio + HOST_CTL);  in mtip_hw_init()
3347 		writel(readl(dd->mmio + HOST_CTL) & ~HOST_IRQ_EN,  in mtip_hw_exit()
3348 				dd->mmio + HOST_CTL);  in mtip_hw_exit()
3413 	writel(readl(dd->mmio + HOST_CTL) & ~HOST_IRQ_EN,  in mtip_hw_suspend()
3414 			dd->mmio + HOST_CTL);  in mtip_hw_suspend()
3452 	writel(readl(dd->mmio + HOST_CTL) | HOST_IRQ_EN,  in mtip_hw_resume()
3453 			dd->mmio + HOST_CTL);  in mtip_hw_resume()
3795 	u32 host_cap_64 = readl(dd->mmio + HOST_CAP) & HOST_CAP_64;  in mtip_init_cmd()