80 #define CCI_PMU_CNTR_BASE(idx)	((idx) * SZ_4K)  argument
236 static int pmu_is_valid_counter(struct cci_pmu *cci_pmu, int idx)  in pmu_is_valid_counter()  argument
238 	return CCI_PMU_CYCLE_CNTR_IDX <= idx &&  in pmu_is_valid_counter()
239 		idx <= CCI_PMU_CNTR_LAST(cci_pmu);  in pmu_is_valid_counter()
242 static u32 pmu_read_register(int idx, unsigned int offset)  in pmu_read_register()  argument
244 	return readl_relaxed(pmu->base + CCI_PMU_CNTR_BASE(idx) + offset);  in pmu_read_register()
247 static void pmu_write_register(u32 value, int idx, unsigned int offset)  in pmu_write_register()  argument
249 	return writel_relaxed(value, pmu->base + CCI_PMU_CNTR_BASE(idx) + offset);  in pmu_write_register()
252 static void pmu_disable_counter(int idx)  in pmu_disable_counter()  argument
254 	pmu_write_register(0, idx, CCI_PMU_CNTR_CTRL);  in pmu_disable_counter()
257 static void pmu_enable_counter(int idx)  in pmu_enable_counter()  argument
259 	pmu_write_register(1, idx, CCI_PMU_CNTR_CTRL);  in pmu_enable_counter()
262 static void pmu_set_event(int idx, unsigned long event)  in pmu_set_event()  argument
264 	pmu_write_register(event, idx, CCI_PMU_EVT_SEL);  in pmu_set_event()
281 	int idx;  in pmu_get_event_idx()  local
290 	for (idx = CCI_PMU_CNTR0_IDX; idx <= CCI_PMU_CNTR_LAST(cci_pmu); ++idx)  in pmu_get_event_idx()
291 		if (!test_and_set_bit(idx, hw->used_mask))  in pmu_get_event_idx()
292 			return idx;  in pmu_get_event_idx()
365 	int idx = hw_counter->idx;  in pmu_read_counter()  local
368 	if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) {  in pmu_read_counter()
369 		dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);  in pmu_read_counter()
372 	value = pmu_read_register(idx, CCI_PMU_CNTR);  in pmu_read_counter()
381 	int idx = hw_counter->idx;  in pmu_write_counter()  local
383 	if (unlikely(!pmu_is_valid_counter(cci_pmu, idx)))  in pmu_write_counter()
384 		dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);  in pmu_write_counter()
386 		pmu_write_register(value, idx, CCI_PMU_CNTR);  in pmu_write_counter()
431 	int idx, handled = IRQ_NONE;  in pmu_handle_irq()  local
439 	for (idx = CCI_PMU_CYCLE_CNTR_IDX; idx <= CCI_PMU_CNTR_LAST(cci_pmu); idx++) {  in pmu_handle_irq()
440 		struct perf_event *event = events->events[idx];  in pmu_handle_irq()
449 		if (!(pmu_read_register(idx, CCI_PMU_OVRFLW) &  in pmu_handle_irq()
453 		pmu_write_register(CCI_PMU_OVRFLW_FLAG, idx, CCI_PMU_OVRFLW);  in pmu_handle_irq()
531 	int idx = hwc->idx;  in cci_pmu_start()  local
543 	if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) {  in cci_pmu_start()
544 		dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);  in cci_pmu_start()
551 	if (idx != CCI_PMU_CYCLE_CNTR_IDX)  in cci_pmu_start()
552 		pmu_set_event(idx, hwc->config_base);  in cci_pmu_start()
555 	pmu_enable_counter(idx);  in cci_pmu_start()
564 	int idx = hwc->idx;  in cci_pmu_stop()  local
569 	if (unlikely(!pmu_is_valid_counter(cci_pmu, idx))) {  in cci_pmu_stop()
570 		dev_err(&cci_pmu->plat_device->dev, "Invalid CCI PMU counter %d\n", idx);  in cci_pmu_stop()
578 	pmu_disable_counter(idx);  in cci_pmu_stop()
588 	int idx;  in cci_pmu_add()  local
594 	idx = pmu_get_event_idx(hw_events, event);  in cci_pmu_add()
595 	if (idx < 0) {  in cci_pmu_add()
596 		err = idx;  in cci_pmu_add()
600 	event->hw.idx = idx;  in cci_pmu_add()
601 	hw_events->events[idx] = event;  in cci_pmu_add()
620 	int idx = hwc->idx;  in cci_pmu_del()  local
623 	hw_events->events[idx] = NULL;  in cci_pmu_del()
624 	clear_bit(idx, hw_events->used_mask);  in cci_pmu_del()
699 	hwc->idx		= -1;  in __hw_perf_event_init()