149 	struct arm_ccn_dt, pmu), struct arm_ccn, dt)
185 	struct arm_ccn_dt dt;  member
439 		return &ccn->dt.cmp_mask[i].l;  in arm_ccn_pmu_get_cmp_mask()
441 		return &ccn->dt.cmp_mask[i].h;  in arm_ccn_pmu_get_cmp_mask()
596 		clear_bit(CCN_IDX_PMU_CYCLE_COUNTER, ccn->dt.pmu_counters_mask);  in arm_ccn_pmu_event_destroy()
599 				ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_event_destroy()
607 		clear_bit(hw->idx, ccn->dt.pmu_counters_mask);  in arm_ccn_pmu_event_destroy()
610 	ccn->dt.pmu_counters[hw->idx].source = NULL;  in arm_ccn_pmu_event_destroy()
611 	ccn->dt.pmu_counters[hw->idx].event = NULL;  in arm_ccn_pmu_event_destroy()
717 				ccn->dt.pmu_counters_mask))  in arm_ccn_pmu_event_init()
721 		ccn->dt.pmu_counters[CCN_IDX_PMU_CYCLE_COUNTER].event = event;  in arm_ccn_pmu_event_init()
727 	hw->idx = arm_ccn_pmu_alloc_bit(ccn->dt.pmu_counters_mask,  in arm_ccn_pmu_event_init()
738 	ccn->dt.pmu_counters[hw->idx].source = source;  in arm_ccn_pmu_event_init()
750 		clear_bit(hw->idx, ccn->dt.pmu_counters_mask);  in arm_ccn_pmu_event_init()
755 	ccn->dt.pmu_counters[hw->idx].event = event;  in arm_ccn_pmu_event_init()
766 		res = readq(ccn->dt.base + CCN_DT_PMCCNTR);  in arm_ccn_pmu_read_counter()
769 		writel(0x1, ccn->dt.base + CCN_DT_PMSR_REQ);  in arm_ccn_pmu_read_counter()
770 		while (!(readl(ccn->dt.base + CCN_DT_PMSR) & 0x1))  in arm_ccn_pmu_read_counter()
772 		writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);  in arm_ccn_pmu_read_counter()
773 		res = readl(ccn->dt.base + CCN_DT_PMCCNTRSR + 4) & 0xff;  in arm_ccn_pmu_read_counter()
775 		res |= readl(ccn->dt.base + CCN_DT_PMCCNTRSR);  in arm_ccn_pmu_read_counter()
778 		res = readl(ccn->dt.base + CCN_DT_PMEVCNT(idx));  in arm_ccn_pmu_read_counter()
818 	spin_lock(&ccn->dt.config_lock);  in arm_ccn_pmu_xp_dt_config()
826 	spin_unlock(&ccn->dt.config_lock);  in arm_ccn_pmu_xp_dt_config()
839 		hrtimer_start(&ccn->dt.hrtimer, arm_ccn_pmu_timer_period(),  in arm_ccn_pmu_event_start()
856 		hrtimer_cancel(&ccn->dt.hrtimer);  in arm_ccn_pmu_event_stop()
876 			ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_xp_watchpoint_config()
881 	u64 mask_l = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].l;  in arm_ccn_pmu_xp_watchpoint_config()
882 	u64 mask_h = ccn->dt.cmp_mask[CCN_CONFIG_MASK(event->attr.config)].h;  in arm_ccn_pmu_xp_watchpoint_config()
924 			ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_xp_event_config()
945 			ccn->dt.pmu_counters[hw->idx].source;  in arm_ccn_pmu_node_event_config()
992 	spin_lock(&ccn->dt.config_lock);  in arm_ccn_pmu_event_config()
996 	val = readl(ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);  in arm_ccn_pmu_event_config()
1000 	writel(val, ccn->dt.base + CCN_DT_ACTIVE_DSM + offset);  in arm_ccn_pmu_event_config()
1012 	spin_unlock(&ccn->dt.config_lock);  in arm_ccn_pmu_event_config()
1039 static irqreturn_t arm_ccn_pmu_overflow_handler(struct arm_ccn_dt *dt)  in arm_ccn_pmu_overflow_handler()  argument
1041 	u32 pmovsr = readl(dt->base + CCN_DT_PMOVSR);  in arm_ccn_pmu_overflow_handler()
1047 	writel(pmovsr, dt->base + CCN_DT_PMOVSR_CLR);  in arm_ccn_pmu_overflow_handler()
1052 		struct perf_event *event = dt->pmu_counters[idx].event;  in arm_ccn_pmu_overflow_handler()
1069 	struct arm_ccn_dt *dt = container_of(hrtimer, struct arm_ccn_dt,  in arm_ccn_pmu_timer_handler()  local
1074 	arm_ccn_pmu_overflow_handler(dt);  in arm_ccn_pmu_timer_handler()
1090 	ccn->dt.base = ccn->base + CCN_REGION_SIZE;  in arm_ccn_pmu_init()
1091 	spin_lock_init(&ccn->dt.config_lock);  in arm_ccn_pmu_init()
1092 	writel(CCN_DT_PMOVSR_CLR__MASK, ccn->dt.base + CCN_DT_PMOVSR_CLR);  in arm_ccn_pmu_init()
1093 	writel(CCN_DT_CTL__DT_EN, ccn->dt.base + CCN_DT_CTL);  in arm_ccn_pmu_init()
1095 			ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_init()
1096 	writel(0x1, ccn->dt.base + CCN_DT_PMSR_CLR);  in arm_ccn_pmu_init()
1106 	ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].l = ~0;  in arm_ccn_pmu_init()
1107 	ccn->dt.cmp_mask[CCN_IDX_MASK_ANY].h = ~0;  in arm_ccn_pmu_init()
1108 	ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].l = 0;  in arm_ccn_pmu_init()
1109 	ccn->dt.cmp_mask[CCN_IDX_MASK_EXACT].h = 0;  in arm_ccn_pmu_init()
1110 	ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].l = ~0;  in arm_ccn_pmu_init()
1111 	ccn->dt.cmp_mask[CCN_IDX_MASK_ORDER].h = ~(0x1 << 15);  in arm_ccn_pmu_init()
1112 	ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].l = ~0;  in arm_ccn_pmu_init()
1113 	ccn->dt.cmp_mask[CCN_IDX_MASK_OPCODE].h = ~(0x1f << 9);  in arm_ccn_pmu_init()
1116 	ccn->dt.id = ida_simple_get(&arm_ccn_pmu_ida, 0, 0, GFP_KERNEL);  in arm_ccn_pmu_init()
1117 	if (ccn->dt.id == 0) {  in arm_ccn_pmu_init()
1120 		int len = snprintf(NULL, 0, "ccn_%d", ccn->dt.id);  in arm_ccn_pmu_init()
1123 		snprintf(name, len + 1, "ccn_%d", ccn->dt.id);  in arm_ccn_pmu_init()
1127 	ccn->dt.pmu = (struct pmu) {  in arm_ccn_pmu_init()
1141 		hrtimer_init(&ccn->dt.hrtimer, CLOCK_MONOTONIC,  in arm_ccn_pmu_init()
1143 		ccn->dt.hrtimer.function = arm_ccn_pmu_timer_handler;  in arm_ccn_pmu_init()
1146 	return perf_pmu_register(&ccn->dt.pmu, name, -1);  in arm_ccn_pmu_init()
1155 	writel(0, ccn->dt.base + CCN_DT_PMCR);  in arm_ccn_pmu_cleanup()
1156 	perf_pmu_unregister(&ccn->dt.pmu);  in arm_ccn_pmu_cleanup()
1157 	ida_simple_remove(&arm_ccn_pmu_ida, ccn->dt.id);  in arm_ccn_pmu_cleanup()
1264 		res = arm_ccn_pmu_overflow_handler(&ccn->dt);  in arm_ccn_irq_handler()