163 				iowrite32(0x01,  /* Message NACK */  in xillybus_isr()
299 	iowrite32(0x03, ep->registers + fpga_msg_ctrl_reg); /* Message ACK */  in xillybus_isr()
378 		iowrite32((u32) (dma_addr & 0xffffffff),  in xilly_get_dma_buffers()
380 		iowrite32(((u32) ((((u64) dma_addr) >> 32) & 0xffffffff)),  in xilly_get_dma_buffers()
388 			iowrite32(s->regdirection | s->nbuffer++,  in xilly_get_dma_buffers()
395 			iowrite32(s->regdirection,  in xilly_get_dma_buffers()
618 	iowrite32(1 |  in xilly_obtain_idt()
780 				iowrite32(1 | (channel->chan_num << 1) |  in xillybus_read()
866 				iowrite32(offsetlimit,  in xillybus_read()
870 				iowrite32(1 | (channel->chan_num << 1) |  in xillybus_read()
959 			iowrite32(1 | (channel->chan_num << 1) |  in xillybus_read()
1078 		iowrite32(end_offset_plus1 - 1,  in xillybus_myflush()
1081 		iowrite32((channel->chan_num << 1) | /* Channel ID */  in xillybus_myflush()
1320 				iowrite32(end_offset_plus1 - 1,  in xillybus_write()
1324 				iowrite32((channel->chan_num << 1) |  in xillybus_write()
1518 			iowrite32(1 | (channel->chan_num << 1) |  in xillybus_open()
1540 			iowrite32((channel->chan_num << 1) |  in xillybus_open()
1584 			iowrite32((channel->chan_num << 1) | /* Channel ID */  in xillybus_release()
1598 			iowrite32(1 | (channel->chan_num << 1) |  in xillybus_release()
1705 	iowrite32(pos >> channel->log2_element_size,  in xillybus_llseek()
1708 	iowrite32((channel->chan_num << 1) |  in xillybus_llseek()
1923 	iowrite32((u32) (endpoint->dma_using_dac & 0x0001),  in xilly_quiesce()
1963 	iowrite32(1, endpoint->registers + fpga_endian_reg);  in xillybus_endpoint_discovery()
1978 	iowrite32(0x04, endpoint->registers + fpga_msg_ctrl_reg);  in xillybus_endpoint_discovery()
1986 	iowrite32((u32) (endpoint->dma_using_dac & 0x0001),  in xillybus_endpoint_discovery()
1998 	iowrite32((u32) (0x0002 | (endpoint->dma_using_dac & 0x0001)),  in xillybus_endpoint_discovery()