Lines Matching refs:divq
108 unsigned long divf, divq, vco_freq, reg; in clk_pll_recalc_rate() local
115 divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT; in clk_pll_recalc_rate()
118 return vco_freq / (1 << divq); in clk_pll_recalc_rate()
124 u32 divq, divf; in clk_pll_calc() local
132 for (divq = 1; divq <= 6; divq++) { in clk_pll_calc()
133 if ((rate * (1 << divq)) >= HB_PLL_VCO_MIN_FREQ) in clk_pll_calc()
137 vco_freq = rate * (1 << divq); in clk_pll_calc()
141 *pdivq = divq; in clk_pll_calc()
148 u32 divq, divf; in clk_pll_round_rate() local
151 clk_pll_calc(rate, ref_freq, &divq, &divf); in clk_pll_round_rate()
153 return (ref_freq * (divf + 1)) / (1 << divq); in clk_pll_round_rate()
160 u32 divq, divf; in clk_pll_set_rate() local
163 clk_pll_calc(rate, parent_rate, &divq, &divf); in clk_pll_set_rate()
173 reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT); in clk_pll_set_rate()
186 reg |= divq << HB_PLL_DIVQ_SHIFT; in clk_pll_set_rate()