50 	void __iomem	*reg;  member
58 	u32 reg;  in clk_pll_prepare()  local
60 	reg = readl(hbclk->reg);  in clk_pll_prepare()
61 	reg &= ~HB_PLL_RESET;  in clk_pll_prepare()
62 	writel(reg, hbclk->reg);  in clk_pll_prepare()
64 	while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)  in clk_pll_prepare()
66 	while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)  in clk_pll_prepare()
75 	u32 reg;  in clk_pll_unprepare()  local
77 	reg = readl(hbclk->reg);  in clk_pll_unprepare()
78 	reg |= HB_PLL_RESET;  in clk_pll_unprepare()
79 	writel(reg, hbclk->reg);  in clk_pll_unprepare()
85 	u32 reg;  in clk_pll_enable()  local
87 	reg = readl(hbclk->reg);  in clk_pll_enable()
88 	reg |= HB_PLL_EXT_ENA;  in clk_pll_enable()
89 	writel(reg, hbclk->reg);  in clk_pll_enable()
97 	u32 reg;  in clk_pll_disable()  local
99 	reg = readl(hbclk->reg);  in clk_pll_disable()
100 	reg &= ~HB_PLL_EXT_ENA;  in clk_pll_disable()
101 	writel(reg, hbclk->reg);  in clk_pll_disable()
108 	unsigned long divf, divq, vco_freq, reg;  in clk_pll_recalc_rate()  local
110 	reg = readl(hbclk->reg);  in clk_pll_recalc_rate()
111 	if (reg & HB_PLL_EXT_BYPASS)  in clk_pll_recalc_rate()
114 	divf = (reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT;  in clk_pll_recalc_rate()
115 	divq = (reg & HB_PLL_DIVQ_MASK) >> HB_PLL_DIVQ_SHIFT;  in clk_pll_recalc_rate()
161 	u32 reg;  in clk_pll_set_rate()  local
165 	reg = readl(hbclk->reg);  in clk_pll_set_rate()
166 	if (divf != ((reg & HB_PLL_DIVF_MASK) >> HB_PLL_DIVF_SHIFT)) {  in clk_pll_set_rate()
168 		reg |= HB_PLL_EXT_BYPASS;  in clk_pll_set_rate()
169 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);  in clk_pll_set_rate()
171 		writel(reg | HB_PLL_RESET, hbclk->reg);  in clk_pll_set_rate()
172 		reg &= ~(HB_PLL_DIVF_MASK | HB_PLL_DIVQ_MASK);  in clk_pll_set_rate()
173 		reg |= (divf << HB_PLL_DIVF_SHIFT) | (divq << HB_PLL_DIVQ_SHIFT);  in clk_pll_set_rate()
174 		writel(reg | HB_PLL_RESET, hbclk->reg);  in clk_pll_set_rate()
175 		writel(reg, hbclk->reg);  in clk_pll_set_rate()
177 		while ((readl(hbclk->reg) & HB_PLL_LOCK) == 0)  in clk_pll_set_rate()
179 		while ((readl(hbclk->reg) & HB_PLL_LOCK_500) == 0)  in clk_pll_set_rate()
181 		reg |= HB_PLL_EXT_ENA;  in clk_pll_set_rate()
182 		reg &= ~HB_PLL_EXT_BYPASS;  in clk_pll_set_rate()
184 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);  in clk_pll_set_rate()
185 		reg &= ~HB_PLL_DIVQ_MASK;  in clk_pll_set_rate()
186 		reg |= divq << HB_PLL_DIVQ_SHIFT;  in clk_pll_set_rate()
187 		writel(reg | HB_PLL_EXT_BYPASS, hbclk->reg);  in clk_pll_set_rate()
189 	writel(reg, hbclk->reg);  in clk_pll_set_rate()
208 	u32 div = (readl(hbclk->reg) & HB_A9_PCLK_DIV) ? 8 : 4;  in clk_cpu_periphclk_recalc_rate()
220 	u32 div = (readl(hbclk->reg) & HB_A9_BCLK_DIV_MASK) >> HB_A9_BCLK_DIV_SHIFT;  in clk_cpu_a9bclk_recalc_rate()
235 	div = readl(hbclk->reg) & 0x1f;  in clk_periclk_recalc_rate()
264 	writel(div >> 1, hbclk->reg);  in clk_periclk_set_rate()
276 	u32 reg;  in hb_clk_init()  local
285 	rc = of_property_read_u32(node, "reg", &reg);  in hb_clk_init()
295 	hb_clk->reg = of_iomap(srnp, 0);  in hb_clk_init()
296 	BUG_ON(!hb_clk->reg);  in hb_clk_init()
297 	hb_clk->reg += reg;  in hb_clk_init()