60 static inline u32 pll_readl(struct pistachio_clk_pll *pll, u32 reg)  in pll_readl()  argument
62 	return readl(pll->base + reg);  in pll_readl()
65 static inline void pll_writel(struct pistachio_clk_pll *pll, u32 val, u32 reg)  in pll_writel()  argument
67 	writel(val, pll->base + reg);  in pll_writel()
84 pll_get_params(struct pistachio_clk_pll *pll, unsigned long fref,  in pll_get_params()  argument
89 	for (i = 0; i < pll->nr_rates; i++) {  in pll_get_params()
90 		if (pll->rates[i].fref == fref && pll->rates[i].fout == fout)  in pll_get_params()
91 			return &pll->rates[i];  in pll_get_params()
100 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_round_rate()  local
103 	for (i = 0; i < pll->nr_rates; i++) {  in pll_round_rate()
104 		if (i > 0 && pll->rates[i].fref == *parent_rate &&  in pll_round_rate()
105 		    pll->rates[i].fout <= rate)  in pll_round_rate()
106 			return pll->rates[i - 1].fout;  in pll_round_rate()
109 	return pll->rates[0].fout;  in pll_round_rate()
114 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_enable()  local
117 	val = pll_readl(pll, PLL_CTRL3);  in pll_gf40lp_frac_enable()
120 	pll_writel(pll, val, PLL_CTRL3);  in pll_gf40lp_frac_enable()
122 	val = pll_readl(pll, PLL_CTRL4);  in pll_gf40lp_frac_enable()
124 	pll_writel(pll, val, PLL_CTRL4);  in pll_gf40lp_frac_enable()
131 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_disable()  local
134 	val = pll_readl(pll, PLL_CTRL3);  in pll_gf40lp_frac_disable()
136 	pll_writel(pll, val, PLL_CTRL3);  in pll_gf40lp_frac_disable()
141 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_is_enabled()  local
143 	return !(pll_readl(pll, PLL_CTRL3) & PLL_FRAC_CTRL3_PD);  in pll_gf40lp_frac_is_enabled()
149 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_set_rate()  local
154 	params = pll_get_params(pll, parent_rate, rate);  in pll_gf40lp_frac_set_rate()
162 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_frac_set_rate()
167 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_frac_set_rate()
169 	val = pll_readl(pll, PLL_CTRL2);  in pll_gf40lp_frac_set_rate()
178 	pll_writel(pll, val, PLL_CTRL2);  in pll_gf40lp_frac_set_rate()
180 	while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))  in pll_gf40lp_frac_set_rate()
192 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_frac_recalc_rate()  local
196 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_frac_recalc_rate()
200 	val = pll_readl(pll, PLL_CTRL2);  in pll_gf40lp_frac_recalc_rate()
231 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_enable()  local
234 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_enable()
237 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_laint_enable()
239 	val = pll_readl(pll, PLL_CTRL2);  in pll_gf40lp_laint_enable()
241 	pll_writel(pll, val, PLL_CTRL2);  in pll_gf40lp_laint_enable()
248 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_disable()  local
251 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_disable()
253 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_laint_disable()
258 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_is_enabled()  local
260 	return !(pll_readl(pll, PLL_CTRL1) & PLL_INT_CTRL1_PD);  in pll_gf40lp_laint_is_enabled()
266 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_set_rate()  local
271 	params = pll_get_params(pll, parent_rate, rate);  in pll_gf40lp_laint_set_rate()
279 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_set_rate()
288 	pll_writel(pll, val, PLL_CTRL1);  in pll_gf40lp_laint_set_rate()
290 	while (!(pll_readl(pll, PLL_STATUS) & PLL_STATUS_LOCK))  in pll_gf40lp_laint_set_rate()
302 	struct pistachio_clk_pll *pll = to_pistachio_pll(hw);  in pll_gf40lp_laint_recalc_rate()  local
306 	val = pll_readl(pll, PLL_CTRL1);  in pll_gf40lp_laint_recalc_rate()
342 	struct pistachio_clk_pll *pll;  in pll_register()  local
346 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in pll_register()
347 	if (!pll)  in pll_register()
370 		kfree(pll);  in pll_register()
374 	pll->hw.init = &init;  in pll_register()
375 	pll->base = base;  in pll_register()
376 	pll->rates = rates;  in pll_register()
377 	pll->nr_rates = nr_rates;  in pll_register()
379 	clk = clk_register(NULL, &pll->hw);  in pll_register()
381 		kfree(pll);  in pll_register()
387 				struct pistachio_pll *pll,  in pistachio_clk_register_pll()  argument
394 		clk = pll_register(pll[i].name, pll[i].parent,  in pistachio_clk_register_pll()
395 				   0, p->base + pll[i].reg_base,  in pistachio_clk_register_pll()
396 				   pll[i].type, pll[i].rates,  in pistachio_clk_register_pll()
397 				   pll[i].nr_rates);  in pistachio_clk_register_pll()
398 		p->clk_data.clks[pll[i].id] = clk;  in pistachio_clk_register_pll()