39 	struct clk_pll *pll = to_clk_pll(hw);  in clk_pll_enable()  local
44 	ret = regmap_read(pll->clkr.regmap, pll->mode_reg, &val);  in clk_pll_enable()
53 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_BYPASSNL,  in clk_pll_enable()
65 	ret = regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_RESET_N,  in clk_pll_enable()
74 	return regmap_update_bits(pll->clkr.regmap, pll->mode_reg, PLL_OUTCTRL,  in clk_pll_enable()
80 	struct clk_pll *pll = to_clk_pll(hw);  in clk_pll_disable()  local
84 	regmap_read(pll->clkr.regmap, pll->mode_reg, &val);  in clk_pll_disable()
89 	regmap_update_bits(pll->clkr.regmap, pll->mode_reg, mask, 0);  in clk_pll_disable()
95 	struct clk_pll *pll = to_clk_pll(hw);  in clk_pll_recalc_rate()  local
100 	regmap_read(pll->clkr.regmap, pll->l_reg, &l);  in clk_pll_recalc_rate()
101 	regmap_read(pll->clkr.regmap, pll->m_reg, &m);  in clk_pll_recalc_rate()
102 	regmap_read(pll->clkr.regmap, pll->n_reg, &n);  in clk_pll_recalc_rate()
115 	if (pll->post_div_width) {  in clk_pll_recalc_rate()
116 		regmap_read(pll->clkr.regmap, pll->config_reg, &config);  in clk_pll_recalc_rate()
117 		config >>= pll->post_div_shift;  in clk_pll_recalc_rate()
118 		config &= BIT(pll->post_div_width) - 1;  in clk_pll_recalc_rate()
143 	struct clk_pll *pll = to_clk_pll(hw);  in clk_pll_determine_rate()  local
146 	f = find_freq(pll->freq_tbl, rate);  in clk_pll_determine_rate()
156 	struct clk_pll *pll = to_clk_pll(hw);  in clk_pll_set_rate()  local
162 	f = find_freq(pll->freq_tbl, rate);  in clk_pll_set_rate()
166 	regmap_read(pll->clkr.regmap, pll->mode_reg, &mode);  in clk_pll_set_rate()
172 	regmap_update_bits(pll->clkr.regmap, pll->l_reg, 0x3ff, f->l);  in clk_pll_set_rate()
173 	regmap_update_bits(pll->clkr.regmap, pll->m_reg, 0x7ffff, f->m);  in clk_pll_set_rate()
174 	regmap_update_bits(pll->clkr.regmap, pll->n_reg, 0x7ffff, f->n);  in clk_pll_set_rate()
175 	regmap_write(pll->clkr.regmap, pll->config_reg, f->ibits);  in clk_pll_set_rate()
192 static int wait_for_pll(struct clk_pll *pll)  in wait_for_pll()  argument
197 	const char *name = __clk_get_name(pll->clkr.hw.clk);  in wait_for_pll()
201 		ret = regmap_read(pll->clkr.regmap, pll->status_reg, &val);  in wait_for_pll()
204 		if (val & BIT(pll->status_bit))  in wait_for_pll()
232 clk_pll_set_fsm_mode(struct clk_pll *pll, struct regmap *regmap, u8 lock_count)  in clk_pll_set_fsm_mode()  argument
238 	regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_RESET, 0);  in clk_pll_set_fsm_mode()
244 	regmap_update_bits(regmap, pll->mode_reg, mask, val);  in clk_pll_set_fsm_mode()
247 	regmap_update_bits(regmap, pll->mode_reg, PLL_VOTE_FSM_ENA,  in clk_pll_set_fsm_mode()
251 static void clk_pll_configure(struct clk_pll *pll, struct regmap *regmap,  in clk_pll_configure()  argument
257 	regmap_write(regmap, pll->l_reg, config->l);  in clk_pll_configure()
258 	regmap_write(regmap, pll->m_reg, config->m);  in clk_pll_configure()
259 	regmap_write(regmap, pll->n_reg, config->n);  in clk_pll_configure()
275 	regmap_update_bits(regmap, pll->config_reg, mask, val);  in clk_pll_configure()
278 void clk_pll_configure_sr(struct clk_pll *pll, struct regmap *regmap,  in clk_pll_configure_sr()  argument
281 	clk_pll_configure(pll, regmap, config);  in clk_pll_configure_sr()
283 		clk_pll_set_fsm_mode(pll, regmap, 8);  in clk_pll_configure_sr()
287 void clk_pll_configure_sr_hpm_lp(struct clk_pll *pll, struct regmap *regmap,  in clk_pll_configure_sr_hpm_lp()  argument
290 	clk_pll_configure(pll, regmap, config);  in clk_pll_configure_sr_hpm_lp()
292 		clk_pll_set_fsm_mode(pll, regmap, 0);  in clk_pll_configure_sr_hpm_lp()