53 			    struct rockchip_clk_pll *pll, unsigned long rate)  in rockchip_get_pll_settings()  argument
55 	const struct rockchip_pll_rate_table  *rate_table = pll->rate_table;  in rockchip_get_pll_settings()
58 	for (i = 0; i < pll->rate_count; i++) {  in rockchip_get_pll_settings()
69 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_pll_round_rate()  local
70 	const struct rockchip_pll_rate_table *rate_table = pll->rate_table;  in rockchip_pll_round_rate()
74 	for (i = 0; i < pll->rate_count; i++) {  in rockchip_pll_round_rate()
88 static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)  in rockchip_pll_wait_lock()  argument
95 		ret = regmap_read(grf, pll->lock_offset, &val);  in rockchip_pll_wait_lock()
102 		if (val & BIT(pll->lock_shift))  in rockchip_pll_wait_lock()
133 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_recalc_rate()  local
137 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_recalc_rate()
144 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));  in rockchip_rk3066_pll_recalc_rate()
147 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));  in rockchip_rk3066_pll_recalc_rate()
161 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_set_rate()  local
165 	struct clk_mux *pll_mux = &pll->pll_mux;  in rockchip_rk3066_pll_set_rate()
166 	const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;  in rockchip_rk3066_pll_set_rate()
181 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3066_pll_set_rate()
199 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_set_rate()
206 	       pll->reg_base + RK3066_PLLCON(0));  in rockchip_rk3066_pll_set_rate()
210 		       pll->reg_base + RK3066_PLLCON(1));  in rockchip_rk3066_pll_set_rate()
213 		       pll->reg_base + RK3066_PLLCON(2));  in rockchip_rk3066_pll_set_rate()
217 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_set_rate()
221 	ret = rockchip_pll_wait_lock(pll);  in rockchip_rk3066_pll_set_rate()
236 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_enable()  local
239 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_enable()
246 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_disable()  local
250 	       pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_disable()
255 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_is_enabled()  local
256 	u32 pllcon = readl(pll->reg_base + RK3066_PLLCON(3));  in rockchip_rk3066_pll_is_enabled()
263 	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);  in rockchip_rk3066_pll_init()  local
269 	if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))  in rockchip_rk3066_pll_init()
273 	rate = rockchip_get_pll_settings(pll, drate);  in rockchip_rk3066_pll_init()
279 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(0));  in rockchip_rk3066_pll_init()
283 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(1));  in rockchip_rk3066_pll_init()
286 	pllcon = readl_relaxed(pll->reg_base + RK3066_PLLCON(2));  in rockchip_rk3066_pll_init()
340 	struct rockchip_clk_pll *pll;  in rockchip_clk_register_pll()  local
353 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in rockchip_clk_register_pll()
354 	if (!pll)  in rockchip_clk_register_pll()
372 		pll->rate_count = len;  in rockchip_clk_register_pll()
373 		pll->rate_table = kmemdup(rate_table,  in rockchip_clk_register_pll()
374 					pll->rate_count *  in rockchip_clk_register_pll()
377 		WARN(!pll->rate_table,  in rockchip_clk_register_pll()
384 		if (!pll->rate_table)  in rockchip_clk_register_pll()
394 	pll->hw.init = &init;  in rockchip_clk_register_pll()
395 	pll->type = pll_type;  in rockchip_clk_register_pll()
396 	pll->reg_base = base + con_offset;  in rockchip_clk_register_pll()
397 	pll->lock_offset = grf_lock_offset;  in rockchip_clk_register_pll()
398 	pll->lock_shift = lock_shift;  in rockchip_clk_register_pll()
399 	pll->flags = clk_pll_flags;  in rockchip_clk_register_pll()
400 	pll->lock = lock;  in rockchip_clk_register_pll()
403 	pll->pll_mux_ops = &clk_mux_ops;  in rockchip_clk_register_pll()
404 	pll_mux = &pll->pll_mux;  in rockchip_clk_register_pll()
415 	pll_clk = clk_register(NULL, &pll->hw);  in rockchip_clk_register_pll()
430 	init.ops = pll->pll_mux_ops;  in rockchip_clk_register_pll()
443 	kfree(pll);  in rockchip_clk_register_pll()