Lines Matching refs:regofs
34 unsigned short regofs; /* register offset */ member
42 unsigned short regofs; /* register offset */ member
77 u32 regcfg2 = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - in pll_clk_recalc_rate()
85 u32 cfg0 = clkc_readl(clk->regofs); in pll_clk_recalc_rate()
149 clkc_writel(reg, clk->regofs); in pll_clk_set_rate()
151 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG1 - SIRFSOC_CLKC_PLL1_CFG0; in pll_clk_set_rate()
154 reg = clk->regofs + SIRFSOC_CLKC_PLL1_CFG2 - SIRFSOC_CLKC_PLL1_CFG0; in pll_clk_set_rate()
217 .regofs = SIRFSOC_CLKC_PLL1_CFG0,
224 .regofs = SIRFSOC_CLKC_PLL2_CFG0,
231 .regofs = SIRFSOC_CLKC_PLL3_CFG0,
298 u32 cfg = clkc_readl(clk->regofs); in dmn_clk_get_parent()
312 u32 cfg = clkc_readl(clk->regofs); in dmn_clk_set_parent()
319 clkc_writel(cfg | parent, clk->regofs); in dmn_clk_set_parent()
321 while (clkc_readl(clk->regofs) & BIT(3)) in dmn_clk_set_parent()
334 u32 cfg = clkc_readl(clk->regofs); in dmn_clk_recalc_rate()
390 reg = clkc_readl(clk->regofs); in dmn_clk_set_rate()
393 clkc_writel(reg, clk->regofs); in dmn_clk_set_rate()
396 while (clkc_readl(clk->regofs) & BIT(25)) in dmn_clk_set_rate()
454 .regofs = SIRFSOC_CLKC_MEM_CFG,
469 .regofs = SIRFSOC_CLKC_SYS_CFG,
483 .regofs = SIRFSOC_CLKC_IO_CFG,
506 .regofs = SIRFSOC_CLKC_CPU_CFG,
533 .regofs = SIRFSOC_CLKC_DSP_CFG,
548 .regofs = SIRFSOC_CLKC_GFX_CFG,
563 .regofs = SIRFSOC_CLKC_MM_CFG,
583 .regofs = SIRFSOC_CLKC_LCD_CFG,
598 .regofs = SIRFSOC_CLKC_LCD_CFG,