223 static void clk_pll_enable_lock(struct tegra_clk_pll *pll)  in clk_pll_enable_lock()  argument
227 	if (!(pll->params->flags & TEGRA_PLL_USE_LOCK))  in clk_pll_enable_lock()
230 	if (!(pll->params->flags & TEGRA_PLL_HAS_LOCK_ENABLE))  in clk_pll_enable_lock()
233 	val = pll_readl_misc(pll);  in clk_pll_enable_lock()
234 	val |= BIT(pll->params->lock_enable_bit_idx);  in clk_pll_enable_lock()
235 	pll_writel_misc(val, pll);  in clk_pll_enable_lock()
238 static int clk_pll_wait_for_lock(struct tegra_clk_pll *pll)  in clk_pll_wait_for_lock()  argument
244 	if (!(pll->params->flags & TEGRA_PLL_USE_LOCK)) {  in clk_pll_wait_for_lock()
245 		udelay(pll->params->lock_delay);  in clk_pll_wait_for_lock()
249 	lock_addr = pll->clk_base;  in clk_pll_wait_for_lock()
250 	if (pll->params->flags & TEGRA_PLL_LOCK_MISC)  in clk_pll_wait_for_lock()
251 		lock_addr += pll->params->misc_reg;  in clk_pll_wait_for_lock()
253 		lock_addr += pll->params->base_reg;  in clk_pll_wait_for_lock()
255 	lock_mask = pll->params->lock_mask;  in clk_pll_wait_for_lock()
257 	for (i = 0; i < pll->params->lock_delay; i++) {  in clk_pll_wait_for_lock()
267 	       __clk_get_name(pll->hw.clk));  in clk_pll_wait_for_lock()
274 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pll_is_enabled()  local
277 	if (pll->params->flags & TEGRA_PLLM) {  in clk_pll_is_enabled()
278 		val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);  in clk_pll_is_enabled()
283 	val = pll_readl_base(pll);  in clk_pll_is_enabled()
290 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in _clk_pll_enable()  local
293 	clk_pll_enable_lock(pll);  in _clk_pll_enable()
295 	val = pll_readl_base(pll);  in _clk_pll_enable()
296 	if (pll->params->flags & TEGRA_PLL_BYPASS)  in _clk_pll_enable()
299 	pll_writel_base(val, pll);  in _clk_pll_enable()
301 	if (pll->params->flags & TEGRA_PLLM) {  in _clk_pll_enable()
302 		val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);  in _clk_pll_enable()
304 		writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);  in _clk_pll_enable()
310 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in _clk_pll_disable()  local
313 	val = pll_readl_base(pll);  in _clk_pll_disable()
314 	if (pll->params->flags & TEGRA_PLL_BYPASS)  in _clk_pll_disable()
317 	pll_writel_base(val, pll);  in _clk_pll_disable()
319 	if (pll->params->flags & TEGRA_PLLM) {  in _clk_pll_disable()
320 		val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);  in _clk_pll_disable()
322 		writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);  in _clk_pll_disable()
328 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pll_enable()  local
332 	if (pll->lock)  in clk_pll_enable()
333 		spin_lock_irqsave(pll->lock, flags);  in clk_pll_enable()
337 	ret = clk_pll_wait_for_lock(pll);  in clk_pll_enable()
339 	if (pll->lock)  in clk_pll_enable()
340 		spin_unlock_irqrestore(pll->lock, flags);  in clk_pll_enable()
347 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pll_disable()  local
350 	if (pll->lock)  in clk_pll_disable()
351 		spin_lock_irqsave(pll->lock, flags);  in clk_pll_disable()
355 	if (pll->lock)  in clk_pll_disable()
356 		spin_unlock_irqrestore(pll->lock, flags);  in clk_pll_disable()
361 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in _p_div_to_hw()  local
362 	struct pdiv_map *p_tohw = pll->params->pdiv_tohw;  in _p_div_to_hw()
377 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in _hw_to_p_div()  local
378 	struct pdiv_map *p_tohw = pll->params->pdiv_tohw;  in _hw_to_p_div()
396 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in _get_table_rate()  local
399 	for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)  in _get_table_rate()
420 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in _calc_rate()  local
459 	if (cfg->m > divm_max(pll) || cfg->n > divn_max(pll) ||  in _calc_rate()
460 	    (1 << p_div) > divp_max(pll)  in _calc_rate()
461 	    || cfg->output_rate > pll->params->vco_max) {  in _calc_rate()
467 	if (pll->params->pdiv_tohw) {  in _calc_rate()
479 static void _update_pll_mnp(struct tegra_clk_pll *pll,  in _update_pll_mnp()  argument
483 	struct tegra_clk_pll_params *params = pll->params;  in _update_pll_mnp()
487 		(pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &  in _update_pll_mnp()
489 		val = pll_override_readl(params->pmc_divp_reg, pll);  in _update_pll_mnp()
490 		val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);  in _update_pll_mnp()
492 		pll_override_writel(val, params->pmc_divp_reg, pll);  in _update_pll_mnp()
494 		val = pll_override_readl(params->pmc_divnm_reg, pll);  in _update_pll_mnp()
495 		val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |  in _update_pll_mnp()
496 			~(divn_mask(pll) << div_nmp->override_divn_shift);  in _update_pll_mnp()
499 		pll_override_writel(val, params->pmc_divnm_reg, pll);  in _update_pll_mnp()
501 		val = pll_readl_base(pll);  in _update_pll_mnp()
503 		val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |  in _update_pll_mnp()
504 			 divp_mask_shifted(pll));  in _update_pll_mnp()
506 		val |= (cfg->m << divm_shift(pll)) |  in _update_pll_mnp()
507 		       (cfg->n << divn_shift(pll)) |  in _update_pll_mnp()
508 		       (cfg->p << divp_shift(pll));  in _update_pll_mnp()
510 		pll_writel_base(val, pll);  in _update_pll_mnp()
514 static void _get_pll_mnp(struct tegra_clk_pll *pll,  in _get_pll_mnp()  argument
518 	struct tegra_clk_pll_params *params = pll->params;  in _get_pll_mnp()
522 		(pll_override_readl(PMC_PLLP_WB0_OVERRIDE, pll) &  in _get_pll_mnp()
524 		val = pll_override_readl(params->pmc_divp_reg, pll);  in _get_pll_mnp()
525 		cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);  in _get_pll_mnp()
527 		val = pll_override_readl(params->pmc_divnm_reg, pll);  in _get_pll_mnp()
528 		cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);  in _get_pll_mnp()
529 		cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);  in _get_pll_mnp()
531 		val = pll_readl_base(pll);  in _get_pll_mnp()
533 		cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);  in _get_pll_mnp()
534 		cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);  in _get_pll_mnp()
535 		cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);  in _get_pll_mnp()
539 static void _update_pll_cpcon(struct tegra_clk_pll *pll,  in _update_pll_cpcon()  argument
545 	val = pll_readl_misc(pll);  in _update_pll_cpcon()
550 	if (pll->params->flags & TEGRA_PLL_SET_LFCON) {  in _update_pll_cpcon()
554 	} else if (pll->params->flags & TEGRA_PLL_SET_DCCON) {  in _update_pll_cpcon()
556 		if (rate >= (pll->params->vco_max >> 1))  in _update_pll_cpcon()
560 	pll_writel_misc(val, pll);  in _update_pll_cpcon()
566 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in _program_pll()  local
574 	_update_pll_mnp(pll, cfg);  in _program_pll()
576 	if (pll->params->flags & TEGRA_PLL_HAS_CPCON)  in _program_pll()
577 		_update_pll_cpcon(pll, cfg, rate);  in _program_pll()
581 		ret = clk_pll_wait_for_lock(pll);  in _program_pll()
590 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pll_set_rate()  local
595 	if (pll->params->flags & TEGRA_PLL_FIXED) {  in clk_pll_set_rate()
596 		if (rate != pll->params->fixed_rate) {  in clk_pll_set_rate()
599 				pll->params->fixed_rate, rate);  in clk_pll_set_rate()
612 	if (pll->lock)  in clk_pll_set_rate()
613 		spin_lock_irqsave(pll->lock, flags);  in clk_pll_set_rate()
615 	_get_pll_mnp(pll, &old_cfg);  in clk_pll_set_rate()
620 	if (pll->lock)  in clk_pll_set_rate()
621 		spin_unlock_irqrestore(pll->lock, flags);  in clk_pll_set_rate()
629 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pll_round_rate()  local
632 	if (pll->params->flags & TEGRA_PLL_FIXED)  in clk_pll_round_rate()
633 		return pll->params->fixed_rate;  in clk_pll_round_rate()
636 	if (pll->params->flags & TEGRA_PLLM)  in clk_pll_round_rate()
649 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pll_recalc_rate()  local
655 	val = pll_readl_base(pll);  in clk_pll_recalc_rate()
657 	if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))  in clk_pll_recalc_rate()
660 	if ((pll->params->flags & TEGRA_PLL_FIXED) &&  in clk_pll_recalc_rate()
663 		if (_get_table_rate(hw, &sel, pll->params->fixed_rate,  in clk_pll_recalc_rate()
669 		return pll->params->fixed_rate;  in clk_pll_recalc_rate()
672 	_get_pll_mnp(pll, &cfg);  in clk_pll_recalc_rate()
688 static int clk_plle_training(struct tegra_clk_pll *pll)  in clk_plle_training()  argument
693 	if (!pll->pmc)  in clk_plle_training()
700 	val = readl(pll->pmc + PMC_SATA_PWRGT);  in clk_plle_training()
702 	writel(val, pll->pmc + PMC_SATA_PWRGT);  in clk_plle_training()
704 	val = readl(pll->pmc + PMC_SATA_PWRGT);  in clk_plle_training()
706 	writel(val, pll->pmc + PMC_SATA_PWRGT);  in clk_plle_training()
708 	val = readl(pll->pmc + PMC_SATA_PWRGT);  in clk_plle_training()
710 	writel(val, pll->pmc + PMC_SATA_PWRGT);  in clk_plle_training()
712 	val = pll_readl_misc(pll);  in clk_plle_training()
716 		val = pll_readl_misc(pll);  in clk_plle_training()
731 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_plle_enable()  local
737 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))  in clk_plle_enable()
742 	val = pll_readl_misc(pll);  in clk_plle_enable()
744 	pll_writel_misc(val, pll);  in clk_plle_enable()
746 	val = pll_readl_misc(pll);  in clk_plle_enable()
748 		err = clk_plle_training(pll);  in clk_plle_enable()
753 	if (pll->params->flags & TEGRA_PLLE_CONFIGURE) {  in clk_plle_enable()
755 		val = pll_readl_base(pll);  in clk_plle_enable()
756 		val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |  in clk_plle_enable()
757 			 divm_mask_shifted(pll));  in clk_plle_enable()
759 		val |= sel.m << divm_shift(pll);  in clk_plle_enable()
760 		val |= sel.n << divn_shift(pll);  in clk_plle_enable()
761 		val |= sel.p << divp_shift(pll);  in clk_plle_enable()
763 		pll_writel_base(val, pll);  in clk_plle_enable()
766 	val = pll_readl_misc(pll);  in clk_plle_enable()
769 	pll_writel_misc(val, pll);  in clk_plle_enable()
771 	val = readl(pll->clk_base + PLLE_SS_CTRL);  in clk_plle_enable()
774 	writel(val, pll->clk_base + PLLE_SS_CTRL);  in clk_plle_enable()
776 	val = pll_readl_base(pll);  in clk_plle_enable()
778 	pll_writel_base(val, pll);  in clk_plle_enable()
780 	clk_pll_wait_for_lock(pll);  in clk_plle_enable()
788 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_plle_recalc_rate()  local
789 	u32 val = pll_readl_base(pll);  in clk_plle_recalc_rate()
793 	divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));  in clk_plle_recalc_rate()
794 	divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));  in clk_plle_recalc_rate()
795 	divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));  in clk_plle_recalc_rate()
876 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pll_iddq_enable()  local
882 	if (pll->lock)  in clk_pll_iddq_enable()
883 		spin_lock_irqsave(pll->lock, flags);  in clk_pll_iddq_enable()
885 	val = pll_readl(pll->params->iddq_reg, pll);  in clk_pll_iddq_enable()
886 	val &= ~BIT(pll->params->iddq_bit_idx);  in clk_pll_iddq_enable()
887 	pll_writel(val, pll->params->iddq_reg, pll);  in clk_pll_iddq_enable()
892 	ret = clk_pll_wait_for_lock(pll);  in clk_pll_iddq_enable()
894 	if (pll->lock)  in clk_pll_iddq_enable()
895 		spin_unlock_irqrestore(pll->lock, flags);  in clk_pll_iddq_enable()
902 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pll_iddq_disable()  local
906 	if (pll->lock)  in clk_pll_iddq_disable()
907 		spin_lock_irqsave(pll->lock, flags);  in clk_pll_iddq_disable()
911 	val = pll_readl(pll->params->iddq_reg, pll);  in clk_pll_iddq_disable()
912 	val |= BIT(pll->params->iddq_bit_idx);  in clk_pll_iddq_disable()
913 	pll_writel(val, pll->params->iddq_reg, pll);  in clk_pll_iddq_disable()
916 	if (pll->lock)  in clk_pll_iddq_disable()
917 		spin_unlock_irqrestore(pll->lock, flags);  in clk_pll_iddq_disable()
924 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in _calc_dynamic_ramp_rate()  local
931 	p = DIV_ROUND_UP(pll->params->vco_min, rate);  in _calc_dynamic_ramp_rate()
932 	cfg->m = _pll_fixed_mdiv(pll->params, parent_rate);  in _calc_dynamic_ramp_rate()
942 	if (cfg->n > divn_max(pll) || cfg->output_rate > pll->params->vco_max)  in _calc_dynamic_ramp_rate()
952 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in _pll_ramp_calc_pll()  local
959 		if (cfg->m != _pll_fixed_mdiv(pll->params, parent_rate)) {  in _pll_ramp_calc_pll()
971 	if (cfg->p >  pll->params->max_p)  in _pll_ramp_calc_pll()
981 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pllxc_set_rate()  local
990 	if (pll->lock)  in clk_pllxc_set_rate()
991 		spin_lock_irqsave(pll->lock, flags);  in clk_pllxc_set_rate()
993 	_get_pll_mnp(pll, &old_cfg);  in clk_pllxc_set_rate()
998 	if (pll->lock)  in clk_pllxc_set_rate()
999 		spin_unlock_irqrestore(pll->lock, flags);  in clk_pllxc_set_rate()
1029 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pllm_set_rate()  local
1033 	if (pll->lock)  in clk_pllm_set_rate()
1034 		spin_lock_irqsave(pll->lock, flags);  in clk_pllm_set_rate()
1050 	_update_pll_mnp(pll, &cfg);  in clk_pllm_set_rate()
1053 	if (pll->lock)  in clk_pllm_set_rate()
1054 		spin_unlock_irqrestore(pll->lock, flags);  in clk_pllm_set_rate()
1059 static void _pllcx_strobe(struct tegra_clk_pll *pll)  in _pllcx_strobe()  argument
1063 	val = pll_readl_misc(pll);  in _pllcx_strobe()
1065 	pll_writel_misc(val, pll);  in _pllcx_strobe()
1069 	pll_writel_misc(val, pll);  in _pllcx_strobe()
1074 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pllc_enable()  local
1079 	if (pll->lock)  in clk_pllc_enable()
1080 		spin_lock_irqsave(pll->lock, flags);  in clk_pllc_enable()
1085 	val = pll_readl_misc(pll);  in clk_pllc_enable()
1087 	pll_writel_misc(val, pll);  in clk_pllc_enable()
1090 	_pllcx_strobe(pll);  in clk_pllc_enable()
1092 	ret = clk_pll_wait_for_lock(pll);  in clk_pllc_enable()
1094 	if (pll->lock)  in clk_pllc_enable()
1095 		spin_unlock_irqrestore(pll->lock, flags);  in clk_pllc_enable()
1102 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in _clk_pllc_disable()  local
1107 	val = pll_readl_misc(pll);  in _clk_pllc_disable()
1109 	pll_writel_misc(val, pll);  in _clk_pllc_disable()
1115 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pllc_disable()  local
1118 	if (pll->lock)  in clk_pllc_disable()
1119 		spin_lock_irqsave(pll->lock, flags);  in clk_pllc_disable()
1123 	if (pll->lock)  in clk_pllc_disable()
1124 		spin_unlock_irqrestore(pll->lock, flags);  in clk_pllc_disable()
1127 static int _pllcx_update_dynamic_coef(struct tegra_clk_pll *pll,  in _pllcx_update_dynamic_coef()  argument
1152 	val = pll_readl_misc(pll);  in _pllcx_update_dynamic_coef()
1156 	pll_writel_misc(val, pll);  in _pllcx_update_dynamic_coef()
1165 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pllc_set_rate()  local
1169 	if (pll->lock)  in clk_pllc_set_rate()
1170 		spin_lock_irqsave(pll->lock, flags);  in clk_pllc_set_rate()
1176 	_get_pll_mnp(pll, &old_cfg);  in clk_pllc_set_rate()
1190 	ret = _pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);  in clk_pllc_set_rate()
1194 	_update_pll_mnp(pll, &cfg);  in clk_pllc_set_rate()
1200 	if (pll->lock)  in clk_pllc_set_rate()
1201 		spin_unlock_irqrestore(pll->lock, flags);  in clk_pllc_set_rate()
1206 static long _pllre_calc_rate(struct tegra_clk_pll *pll,  in _pllre_calc_rate()  argument
1213 	m = _pll_fixed_mdiv(pll->params, parent_rate);  in _pllre_calc_rate()
1231 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pllre_set_rate()  local
1235 	if (pll->lock)  in clk_pllre_set_rate()
1236 		spin_lock_irqsave(pll->lock, flags);  in clk_pllre_set_rate()
1238 	_pllre_calc_rate(pll, &cfg, rate, parent_rate);  in clk_pllre_set_rate()
1239 	_get_pll_mnp(pll, &old_cfg);  in clk_pllre_set_rate()
1247 		_update_pll_mnp(pll, &cfg);  in clk_pllre_set_rate()
1251 			ret = clk_pll_wait_for_lock(pll);  in clk_pllre_set_rate()
1255 	if (pll->lock)  in clk_pllre_set_rate()
1256 		spin_unlock_irqrestore(pll->lock, flags);  in clk_pllre_set_rate()
1265 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pllre_recalc_rate()  local
1268 	_get_pll_mnp(pll, &cfg);  in clk_pllre_recalc_rate()
1279 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_pllre_round_rate()  local
1281 	return _pllre_calc_rate(pll, NULL, rate, *prate);  in clk_pllre_round_rate()
1286 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_plle_tegra114_enable()  local
1293 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))  in clk_plle_tegra114_enable()
1296 	if (pll->lock)  in clk_plle_tegra114_enable()
1297 		spin_lock_irqsave(pll->lock, flags);  in clk_plle_tegra114_enable()
1299 	val = pll_readl_base(pll);  in clk_plle_tegra114_enable()
1301 	pll_writel_base(val, pll);  in clk_plle_tegra114_enable()
1303 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1306 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1309 	val = pll_readl_misc(pll);  in clk_plle_tegra114_enable()
1315 	pll_writel_misc(val, pll);  in clk_plle_tegra114_enable()
1318 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1320 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1322 	val = pll_readl_base(pll);  in clk_plle_tegra114_enable()
1323 	val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |  in clk_plle_tegra114_enable()
1324 		 divm_mask_shifted(pll));  in clk_plle_tegra114_enable()
1326 	val |= sel.m << divm_shift(pll);  in clk_plle_tegra114_enable()
1327 	val |= sel.n << divn_shift(pll);  in clk_plle_tegra114_enable()
1329 	pll_writel_base(val, pll);  in clk_plle_tegra114_enable()
1333 	ret = clk_pll_wait_for_lock(pll);  in clk_plle_tegra114_enable()
1338 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1342 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1344 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1347 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1351 	val = pll_readl_misc(pll);  in clk_plle_tegra114_enable()
1353 	pll_writel_misc(val, pll);  in clk_plle_tegra114_enable()
1355 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1358 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1361 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1363 	val = pll_readl(XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1368 	pll_writel(val, XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1371 	pll_writel(val, XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1374 	val = pll_readl(SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1378 	pll_writel(val, SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1382 	val = pll_readl(SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1384 	pll_writel(val, SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1387 	if (pll->lock)  in clk_plle_tegra114_enable()
1388 		spin_unlock_irqrestore(pll->lock, flags);  in clk_plle_tegra114_enable()
1395 	struct tegra_clk_pll *pll = to_clk_pll(hw);  in clk_plle_tegra114_disable()  local
1399 	if (pll->lock)  in clk_plle_tegra114_disable()
1400 		spin_lock_irqsave(pll->lock, flags);  in clk_plle_tegra114_disable()
1404 	val = pll_readl_misc(pll);  in clk_plle_tegra114_disable()
1406 	pll_writel_misc(val, pll);  in clk_plle_tegra114_disable()
1409 	if (pll->lock)  in clk_plle_tegra114_disable()
1410 		spin_unlock_irqrestore(pll->lock, flags);  in clk_plle_tegra114_disable()
1418 	struct tegra_clk_pll *pll;  in _tegra_init_pll()  local
1420 	pll = kzalloc(sizeof(*pll), GFP_KERNEL);  in _tegra_init_pll()
1421 	if (!pll)  in _tegra_init_pll()
1424 	pll->clk_base = clk_base;  in _tegra_init_pll()
1425 	pll->pmc = pmc;  in _tegra_init_pll()
1427 	pll->params = pll_params;  in _tegra_init_pll()
1428 	pll->lock = lock;  in _tegra_init_pll()
1433 	return pll;  in _tegra_init_pll()
1436 static struct clk *_tegra_clk_register_pll(struct tegra_clk_pll *pll,  in _tegra_clk_register_pll()  argument
1449 	pll->hw.init = &init;  in _tegra_clk_register_pll()
1451 	return clk_register(NULL, &pll->hw);  in _tegra_clk_register_pll()
1459 	struct tegra_clk_pll *pll;  in tegra_clk_register_pll()  local
1464 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pll()
1465 	if (IS_ERR(pll))  in tegra_clk_register_pll()
1466 		return ERR_CAST(pll);  in tegra_clk_register_pll()
1468 	clk = _tegra_clk_register_pll(pll, name, parent_name, flags,  in tegra_clk_register_pll()
1471 		kfree(pll);  in tegra_clk_register_pll()
1490 	struct tegra_clk_pll *pll;  in tegra_clk_register_plle()  local
1499 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_plle()
1500 	if (IS_ERR(pll))  in tegra_clk_register_plle()
1501 		return ERR_CAST(pll);  in tegra_clk_register_plle()
1503 	clk = _tegra_clk_register_pll(pll, name, parent_name, flags,  in tegra_clk_register_plle()
1506 		kfree(pll);  in tegra_clk_register_plle()
1564 	struct tegra_clk_pll *pll;  in tegra_clk_register_pllxc()  local
1599 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllxc()
1600 	if (IS_ERR(pll))  in tegra_clk_register_pllxc()
1601 		return ERR_CAST(pll);  in tegra_clk_register_pllxc()
1603 	clk = _tegra_clk_register_pll(pll, name, parent_name, flags,  in tegra_clk_register_pllxc()
1606 		kfree(pll);  in tegra_clk_register_pllxc()
1618 	struct tegra_clk_pll *pll;  in tegra_clk_register_pllre()  local
1625 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllre()
1626 	if (IS_ERR(pll))  in tegra_clk_register_pllre()
1627 		return ERR_CAST(pll);  in tegra_clk_register_pllre()
1631 	val = pll_readl_base(pll);  in tegra_clk_register_pllre()
1638 		val = m << divm_shift(pll);  in tegra_clk_register_pllre()
1639 		val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);  in tegra_clk_register_pllre()
1640 		pll_writel_base(val, pll);  in tegra_clk_register_pllre()
1645 	val = pll_readl_misc(pll);  in tegra_clk_register_pllre()
1647 	pll_writel_misc(val, pll);  in tegra_clk_register_pllre()
1649 	clk = _tegra_clk_register_pll(pll, name, parent_name, flags,  in tegra_clk_register_pllre()
1652 		kfree(pll);  in tegra_clk_register_pllre()
1663 	struct tegra_clk_pll *pll;  in tegra_clk_register_pllm()  local
1684 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllm()
1685 	if (IS_ERR(pll))  in tegra_clk_register_pllm()
1686 		return ERR_CAST(pll);  in tegra_clk_register_pllm()
1688 	clk = _tegra_clk_register_pll(pll, name, parent_name, flags,  in tegra_clk_register_pllm()
1691 		kfree(pll);  in tegra_clk_register_pllm()
1704 	struct tegra_clk_pll *pll;  in tegra_clk_register_pllc()  local
1723 	pll = _tegra_init_pll(clk_base, pmc, pll_params, lock);  in tegra_clk_register_pllc()
1724 	if (IS_ERR(pll))  in tegra_clk_register_pllc()
1725 		return ERR_CAST(pll);  in tegra_clk_register_pllc()
1752 	pll_writel_base(0, pll);  in tegra_clk_register_pllc()
1753 	_update_pll_mnp(pll, &cfg);  in tegra_clk_register_pllc()
1755 	pll_writel_misc(PLLCX_MISC_DEFAULT, pll);  in tegra_clk_register_pllc()
1756 	pll_writel(PLLCX_MISC1_DEFAULT, pll_params->ext_misc_reg[0], pll);  in tegra_clk_register_pllc()
1757 	pll_writel(PLLCX_MISC2_DEFAULT, pll_params->ext_misc_reg[1], pll);  in tegra_clk_register_pllc()
1758 	pll_writel(PLLCX_MISC3_DEFAULT, pll_params->ext_misc_reg[2], pll);  in tegra_clk_register_pllc()
1760 	_pllcx_update_dynamic_coef(pll, parent_rate, cfg.n);  in tegra_clk_register_pllc()
1762 	clk = _tegra_clk_register_pll(pll, name, parent_name, flags,  in tegra_clk_register_pllc()
1765 		kfree(pll);  in tegra_clk_register_pllc()
1776 	struct tegra_clk_pll *pll;  in tegra_clk_register_plle_tegra114()  local
1781 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_plle_tegra114()
1782 	if (IS_ERR(pll))  in tegra_clk_register_plle_tegra114()
1783 		return ERR_CAST(pll);  in tegra_clk_register_plle_tegra114()
1787 	val = pll_readl_base(pll);  in tegra_clk_register_plle_tegra114()
1788 	val_aux = pll_readl(pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra114()
1798 		pll_writel(val_aux, pll_params->aux_reg, pll);  in tegra_clk_register_plle_tegra114()
1801 	clk = _tegra_clk_register_pll(pll, name, parent_name, flags,  in tegra_clk_register_plle_tegra114()
1804 		kfree(pll);  in tegra_clk_register_plle_tegra114()
1825 	struct tegra_clk_pll *pll;  in tegra_clk_register_pllss()  local
1843 	pll = _tegra_init_pll(clk_base, NULL, pll_params, lock);  in tegra_clk_register_pllss()
1844 	if (IS_ERR(pll))  in tegra_clk_register_pllss()
1845 		return ERR_CAST(pll);  in tegra_clk_register_pllss()
1847 	val = pll_readl_base(pll);  in tegra_clk_register_pllss()
1849 	pll_writel_base(val, pll);  in tegra_clk_register_pllss()
1863 		kfree(pll);  in tegra_clk_register_pllss()
1869 	_update_pll_mnp(pll, &cfg);  in tegra_clk_register_pllss()
1871 	pll_writel_misc(PLLSS_MISC_DEFAULT, pll);  in tegra_clk_register_pllss()
1872 	pll_writel(PLLSS_CFG_DEFAULT, pll_params->ext_misc_reg[0], pll);  in tegra_clk_register_pllss()
1873 	pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[1], pll);  in tegra_clk_register_pllss()
1874 	pll_writel(PLLSS_CTRL1_DEFAULT, pll_params->ext_misc_reg[2], pll);  in tegra_clk_register_pllss()
1876 	val = pll_readl_base(pll);  in tegra_clk_register_pllss()
1880 			kfree(pll);  in tegra_clk_register_pllss()
1887 	pll_writel_base(val, pll);  in tegra_clk_register_pllss()
1889 	clk = _tegra_clk_register_pll(pll, name, parent_name, flags,  in tegra_clk_register_pllss()
1893 		kfree(pll);  in tegra_clk_register_pllss()