397 	struct tegra_clk_pll_freq_table *sel;  in _get_table_rate()  local
399 	for (sel = pll->params->freq_table; sel->input_rate != 0; sel++)  in _get_table_rate()
400 		if (sel->input_rate == parent_rate &&  in _get_table_rate()
401 		    sel->output_rate == rate)  in _get_table_rate()
404 	if (sel->input_rate == 0)  in _get_table_rate()
407 	cfg->input_rate = sel->input_rate;  in _get_table_rate()
408 	cfg->output_rate = sel->output_rate;  in _get_table_rate()
409 	cfg->m = sel->m;  in _get_table_rate()
410 	cfg->n = sel->n;  in _get_table_rate()
411 	cfg->p = sel->p;  in _get_table_rate()
412 	cfg->cpcon = sel->cpcon;  in _get_table_rate()
662 		struct tegra_clk_pll_freq_table sel;  in clk_pll_recalc_rate()  local
663 		if (_get_table_rate(hw, &sel, pll->params->fixed_rate,  in clk_pll_recalc_rate()
733 	struct tegra_clk_pll_freq_table sel;  in clk_plle_enable()  local
737 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))  in clk_plle_enable()
759 		val |= sel.m << divm_shift(pll);  in clk_plle_enable()
760 		val |= sel.n << divn_shift(pll);  in clk_plle_enable()
761 		val |= sel.p << divp_shift(pll);  in clk_plle_enable()
762 		val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;  in clk_plle_enable()
1287 	struct tegra_clk_pll_freq_table sel;  in clk_plle_tegra114_enable()  local
1293 	if (_get_table_rate(hw, &sel, pll->params->fixed_rate, input_rate))  in clk_plle_tegra114_enable()
1326 	val |= sel.m << divm_shift(pll);  in clk_plle_tegra114_enable()
1327 	val |= sel.n << divn_shift(pll);  in clk_plle_tegra114_enable()
1328 	val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;  in clk_plle_tegra114_enable()