191 #define pll_writel(val, offset, p) writel_relaxed(val, p->clk_base + offset)  argument
192 #define pll_writel_base(val, p) pll_writel(val, p->params->base_reg, p)  argument
193 #define pll_writel_misc(val, p) pll_writel(val, p->params->misc_reg, p)  argument
194 #define pll_override_writel(val, offset, p) writel(val, p->pmc + offset)  argument
225 	u32 val;  in clk_pll_enable_lock()  local
233 	val = pll_readl_misc(pll);  in clk_pll_enable_lock()
234 	val |= BIT(pll->params->lock_enable_bit_idx);  in clk_pll_enable_lock()
235 	pll_writel_misc(val, pll);  in clk_pll_enable_lock()
241 	u32 val, lock_mask;  in clk_pll_wait_for_lock()  local
258 		val = readl_relaxed(lock_addr);  in clk_pll_wait_for_lock()
259 		if ((val & lock_mask) == lock_mask) {  in clk_pll_wait_for_lock()
275 	u32 val;  in clk_pll_is_enabled()  local
278 		val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);  in clk_pll_is_enabled()
279 		if (val & PMC_PLLP_WB0_OVERRIDE_PLLM_OVERRIDE)  in clk_pll_is_enabled()
280 			return val & PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE ? 1 : 0;  in clk_pll_is_enabled()
283 	val = pll_readl_base(pll);  in clk_pll_is_enabled()
285 	return val & PLL_BASE_ENABLE ? 1 : 0;  in clk_pll_is_enabled()
291 	u32 val;  in _clk_pll_enable()  local
295 	val = pll_readl_base(pll);  in _clk_pll_enable()
297 		val &= ~PLL_BASE_BYPASS;  in _clk_pll_enable()
298 	val |= PLL_BASE_ENABLE;  in _clk_pll_enable()
299 	pll_writel_base(val, pll);  in _clk_pll_enable()
302 		val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);  in _clk_pll_enable()
303 		val |= PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;  in _clk_pll_enable()
304 		writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);  in _clk_pll_enable()
311 	u32 val;  in _clk_pll_disable()  local
313 	val = pll_readl_base(pll);  in _clk_pll_disable()
315 		val &= ~PLL_BASE_BYPASS;  in _clk_pll_disable()
316 	val &= ~PLL_BASE_ENABLE;  in _clk_pll_disable()
317 	pll_writel_base(val, pll);  in _clk_pll_disable()
320 		val = readl_relaxed(pll->pmc + PMC_PLLP_WB0_OVERRIDE);  in _clk_pll_disable()
321 		val &= ~PMC_PLLP_WB0_OVERRIDE_PLLM_ENABLE;  in _clk_pll_disable()
322 		writel_relaxed(val, pll->pmc + PMC_PLLP_WB0_OVERRIDE);  in _clk_pll_disable()
482 	u32 val;  in _update_pll_mnp()  local
489 		val = pll_override_readl(params->pmc_divp_reg, pll);  in _update_pll_mnp()
490 		val &= ~(divp_mask(pll) << div_nmp->override_divp_shift);  in _update_pll_mnp()
491 		val |= cfg->p << div_nmp->override_divp_shift;  in _update_pll_mnp()
492 		pll_override_writel(val, params->pmc_divp_reg, pll);  in _update_pll_mnp()
494 		val = pll_override_readl(params->pmc_divnm_reg, pll);  in _update_pll_mnp()
495 		val &= ~(divm_mask(pll) << div_nmp->override_divm_shift) |  in _update_pll_mnp()
497 		val |= (cfg->m << div_nmp->override_divm_shift) |  in _update_pll_mnp()
499 		pll_override_writel(val, params->pmc_divnm_reg, pll);  in _update_pll_mnp()
501 		val = pll_readl_base(pll);  in _update_pll_mnp()
503 		val &= ~(divm_mask_shifted(pll) | divn_mask_shifted(pll) |  in _update_pll_mnp()
506 		val |= (cfg->m << divm_shift(pll)) |  in _update_pll_mnp()
510 		pll_writel_base(val, pll);  in _update_pll_mnp()
517 	u32 val;  in _get_pll_mnp()  local
524 		val = pll_override_readl(params->pmc_divp_reg, pll);  in _get_pll_mnp()
525 		cfg->p = (val >> div_nmp->override_divp_shift) & divp_mask(pll);  in _get_pll_mnp()
527 		val = pll_override_readl(params->pmc_divnm_reg, pll);  in _get_pll_mnp()
528 		cfg->m = (val >> div_nmp->override_divm_shift) & divm_mask(pll);  in _get_pll_mnp()
529 		cfg->n = (val >> div_nmp->override_divn_shift) & divn_mask(pll);  in _get_pll_mnp()
531 		val = pll_readl_base(pll);  in _get_pll_mnp()
533 		cfg->m = (val >> div_nmp->divm_shift) & divm_mask(pll);  in _get_pll_mnp()
534 		cfg->n = (val >> div_nmp->divn_shift) & divn_mask(pll);  in _get_pll_mnp()
535 		cfg->p = (val >> div_nmp->divp_shift) & divp_mask(pll);  in _get_pll_mnp()
543 	u32 val;  in _update_pll_cpcon()  local
545 	val = pll_readl_misc(pll);  in _update_pll_cpcon()
547 	val &= ~(PLL_MISC_CPCON_MASK << PLL_MISC_CPCON_SHIFT);  in _update_pll_cpcon()
548 	val |= cfg->cpcon << PLL_MISC_CPCON_SHIFT;  in _update_pll_cpcon()
551 		val &= ~(PLL_MISC_LFCON_MASK << PLL_MISC_LFCON_SHIFT);  in _update_pll_cpcon()
553 			val |= 1 << PLL_MISC_LFCON_SHIFT;  in _update_pll_cpcon()
555 		val &= ~(1 << PLL_MISC_DCCON_SHIFT);  in _update_pll_cpcon()
557 			val |= 1 << PLL_MISC_DCCON_SHIFT;  in _update_pll_cpcon()
560 	pll_writel_misc(val, pll);  in _update_pll_cpcon()
651 	u32 val;  in clk_pll_recalc_rate()  local
655 	val = pll_readl_base(pll);  in clk_pll_recalc_rate()
657 	if ((pll->params->flags & TEGRA_PLL_BYPASS) && (val & PLL_BASE_BYPASS))  in clk_pll_recalc_rate()
661 			!(val & PLL_BASE_OVERRIDE)) {  in clk_pll_recalc_rate()
690 	u32 val;  in clk_plle_training()  local
700 	val = readl(pll->pmc + PMC_SATA_PWRGT);  in clk_plle_training()
701 	val |= PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;  in clk_plle_training()
702 	writel(val, pll->pmc + PMC_SATA_PWRGT);  in clk_plle_training()
704 	val = readl(pll->pmc + PMC_SATA_PWRGT);  in clk_plle_training()
705 	val |= PMC_SATA_PWRGT_PLLE_IDDQ_SWCTL;  in clk_plle_training()
706 	writel(val, pll->pmc + PMC_SATA_PWRGT);  in clk_plle_training()
708 	val = readl(pll->pmc + PMC_SATA_PWRGT);  in clk_plle_training()
709 	val &= ~PMC_SATA_PWRGT_PLLE_IDDQ_VALUE;  in clk_plle_training()
710 	writel(val, pll->pmc + PMC_SATA_PWRGT);  in clk_plle_training()
712 	val = pll_readl_misc(pll);  in clk_plle_training()
716 		val = pll_readl_misc(pll);  in clk_plle_training()
717 		if (val & PLLE_MISC_READY)  in clk_plle_training()
734 	u32 val;  in clk_plle_enable()  local
742 	val = pll_readl_misc(pll);  in clk_plle_enable()
743 	val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);  in clk_plle_enable()
744 	pll_writel_misc(val, pll);  in clk_plle_enable()
746 	val = pll_readl_misc(pll);  in clk_plle_enable()
747 	if (!(val & PLLE_MISC_READY)) {  in clk_plle_enable()
755 		val = pll_readl_base(pll);  in clk_plle_enable()
756 		val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |  in clk_plle_enable()
758 		val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);  in clk_plle_enable()
759 		val |= sel.m << divm_shift(pll);  in clk_plle_enable()
760 		val |= sel.n << divn_shift(pll);  in clk_plle_enable()
761 		val |= sel.p << divp_shift(pll);  in clk_plle_enable()
762 		val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;  in clk_plle_enable()
763 		pll_writel_base(val, pll);  in clk_plle_enable()
766 	val = pll_readl_misc(pll);  in clk_plle_enable()
767 	val |= PLLE_MISC_SETUP_VALUE;  in clk_plle_enable()
768 	val |= PLLE_MISC_LOCK_ENABLE;  in clk_plle_enable()
769 	pll_writel_misc(val, pll);  in clk_plle_enable()
771 	val = readl(pll->clk_base + PLLE_SS_CTRL);  in clk_plle_enable()
772 	val &= ~PLLE_SS_COEFFICIENTS_MASK;  in clk_plle_enable()
773 	val |= PLLE_SS_DISABLE;  in clk_plle_enable()
774 	writel(val, pll->clk_base + PLLE_SS_CTRL);  in clk_plle_enable()
776 	val = pll_readl_base(pll);  in clk_plle_enable()
777 	val |= (PLL_BASE_BYPASS | PLL_BASE_ENABLE);  in clk_plle_enable()
778 	pll_writel_base(val, pll);  in clk_plle_enable()
789 	u32 val = pll_readl_base(pll);  in clk_plle_recalc_rate()  local
793 	divp = (val >> pll->params->div_nmp->divp_shift) & (divp_mask(pll));  in clk_plle_recalc_rate()
794 	divn = (val >> pll->params->div_nmp->divn_shift) & (divn_mask(pll));  in clk_plle_recalc_rate()
795 	divm = (val >> pll->params->div_nmp->divm_shift) & (divm_mask(pll));  in clk_plle_recalc_rate()
842 	u32 val;  in _setup_dynamic_ramp()  local
867 	val = step_a << pll_params->stepa_shift;  in _setup_dynamic_ramp()
868 	val |= step_b << pll_params->stepb_shift;  in _setup_dynamic_ramp()
869 	writel_relaxed(val, clk_base + pll_params->dyn_ramp_reg);  in _setup_dynamic_ramp()
879 	u32 val;  in clk_pll_iddq_enable()  local
885 	val = pll_readl(pll->params->iddq_reg, pll);  in clk_pll_iddq_enable()
886 	val &= ~BIT(pll->params->iddq_bit_idx);  in clk_pll_iddq_enable()
887 	pll_writel(val, pll->params->iddq_reg, pll);  in clk_pll_iddq_enable()
904 	u32 val;  in clk_pll_iddq_disable()  local
911 	val = pll_readl(pll->params->iddq_reg, pll);  in clk_pll_iddq_disable()
912 	val |= BIT(pll->params->iddq_bit_idx);  in clk_pll_iddq_disable()
913 	pll_writel(val, pll->params->iddq_reg, pll);  in clk_pll_iddq_disable()
1061 	u32 val;  in _pllcx_strobe()  local
1063 	val = pll_readl_misc(pll);  in _pllcx_strobe()
1064 	val |= PLLCX_MISC_STROBE;  in _pllcx_strobe()
1065 	pll_writel_misc(val, pll);  in _pllcx_strobe()
1068 	val &= ~PLLCX_MISC_STROBE;  in _pllcx_strobe()
1069 	pll_writel_misc(val, pll);  in _pllcx_strobe()
1075 	u32 val;  in clk_pllc_enable()  local
1085 	val = pll_readl_misc(pll);  in clk_pllc_enable()
1086 	val &= ~PLLCX_MISC_RESET;  in clk_pllc_enable()
1087 	pll_writel_misc(val, pll);  in clk_pllc_enable()
1103 	u32 val;  in _clk_pllc_disable()  local
1107 	val = pll_readl_misc(pll);  in _clk_pllc_disable()
1108 	val |= PLLCX_MISC_RESET;  in _clk_pllc_disable()
1109 	pll_writel_misc(val, pll);  in _clk_pllc_disable()
1130 	u32 val, n_threshold;  in _pllcx_update_dynamic_coef()  local
1152 	val = pll_readl_misc(pll);  in _pllcx_update_dynamic_coef()
1153 	val &= ~(PLLCX_MISC_SDM_DIV_MASK | PLLCX_MISC_FILT_DIV_MASK);  in _pllcx_update_dynamic_coef()
1154 	val |= n <= n_threshold ?  in _pllcx_update_dynamic_coef()
1156 	pll_writel_misc(val, pll);  in _pllcx_update_dynamic_coef()
1288 	u32 val;  in clk_plle_tegra114_enable()  local
1299 	val = pll_readl_base(pll);  in clk_plle_tegra114_enable()
1300 	val &= ~BIT(29); /* Disable lock override */  in clk_plle_tegra114_enable()
1301 	pll_writel_base(val, pll);  in clk_plle_tegra114_enable()
1303 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1304 	val |= PLLE_AUX_ENABLE_SWCTL;  in clk_plle_tegra114_enable()
1305 	val &= ~PLLE_AUX_SEQ_ENABLE;  in clk_plle_tegra114_enable()
1306 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1309 	val = pll_readl_misc(pll);  in clk_plle_tegra114_enable()
1310 	val |= PLLE_MISC_LOCK_ENABLE;  in clk_plle_tegra114_enable()
1311 	val |= PLLE_MISC_IDDQ_SW_CTRL;  in clk_plle_tegra114_enable()
1312 	val &= ~PLLE_MISC_IDDQ_SW_VALUE;  in clk_plle_tegra114_enable()
1313 	val |= PLLE_MISC_PLLE_PTS;  in clk_plle_tegra114_enable()
1314 	val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK;  in clk_plle_tegra114_enable()
1315 	pll_writel_misc(val, pll);  in clk_plle_tegra114_enable()
1318 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1319 	val |= PLLE_SS_DISABLE;  in clk_plle_tegra114_enable()
1320 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1322 	val = pll_readl_base(pll);  in clk_plle_tegra114_enable()
1323 	val &= ~(divp_mask_shifted(pll) | divn_mask_shifted(pll) |  in clk_plle_tegra114_enable()
1325 	val &= ~(PLLE_BASE_DIVCML_MASK << PLLE_BASE_DIVCML_SHIFT);  in clk_plle_tegra114_enable()
1326 	val |= sel.m << divm_shift(pll);  in clk_plle_tegra114_enable()
1327 	val |= sel.n << divn_shift(pll);  in clk_plle_tegra114_enable()
1328 	val |= sel.cpcon << PLLE_BASE_DIVCML_SHIFT;  in clk_plle_tegra114_enable()
1329 	pll_writel_base(val, pll);  in clk_plle_tegra114_enable()
1338 	val = pll_readl(PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1339 	val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT);  in clk_plle_tegra114_enable()
1340 	val &= ~PLLE_SS_COEFFICIENTS_MASK;  in clk_plle_tegra114_enable()
1341 	val |= PLLE_SS_COEFFICIENTS_VAL;  in clk_plle_tegra114_enable()
1342 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1343 	val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS);  in clk_plle_tegra114_enable()
1344 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1346 	val &= ~PLLE_SS_CNTL_INTERP_RESET;  in clk_plle_tegra114_enable()
1347 	pll_writel(val, PLLE_SS_CTRL, pll);  in clk_plle_tegra114_enable()
1351 	val = pll_readl_misc(pll);  in clk_plle_tegra114_enable()
1352 	val &= ~PLLE_MISC_IDDQ_SW_CTRL;  in clk_plle_tegra114_enable()
1353 	pll_writel_misc(val, pll);  in clk_plle_tegra114_enable()
1355 	val = pll_readl(pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1356 	val |= (PLLE_AUX_USE_LOCKDET | PLLE_AUX_SEQ_START_STATE);  in clk_plle_tegra114_enable()
1357 	val &= ~(PLLE_AUX_ENABLE_SWCTL | PLLE_AUX_SS_SWCTL);  in clk_plle_tegra114_enable()
1358 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1360 	val |= PLLE_AUX_SEQ_ENABLE;  in clk_plle_tegra114_enable()
1361 	pll_writel(val, pll->params->aux_reg, pll);  in clk_plle_tegra114_enable()
1363 	val = pll_readl(XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1364 	val |= (XUSBIO_PLL_CFG0_PADPLL_USE_LOCKDET |  in clk_plle_tegra114_enable()
1366 	val &= ~(XUSBIO_PLL_CFG0_CLK_ENABLE_SWCTL |  in clk_plle_tegra114_enable()
1368 	pll_writel(val, XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1370 	val |= XUSBIO_PLL_CFG0_SEQ_ENABLE;  in clk_plle_tegra114_enable()
1371 	pll_writel(val, XUSBIO_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1374 	val = pll_readl(SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1375 	val &= ~SATA_PLL_CFG0_PADPLL_RESET_SWCTL;  in clk_plle_tegra114_enable()
1376 	val |= SATA_PLL_CFG0_PADPLL_USE_LOCKDET;  in clk_plle_tegra114_enable()
1377 	val |= SATA_PLL_CFG0_SEQ_START_STATE;  in clk_plle_tegra114_enable()
1378 	pll_writel(val, SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1382 	val = pll_readl(SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1383 	val |= SATA_PLL_CFG0_SEQ_ENABLE;  in clk_plle_tegra114_enable()
1384 	pll_writel(val, SATA_PLL_CFG0, pll);  in clk_plle_tegra114_enable()
1397 	u32 val;  in clk_plle_tegra114_disable()  local
1404 	val = pll_readl_misc(pll);  in clk_plle_tegra114_disable()
1405 	val |= PLLE_MISC_IDDQ_SW_CTRL | PLLE_MISC_IDDQ_SW_VALUE;  in clk_plle_tegra114_disable()
1406 	pll_writel_misc(val, pll);  in clk_plle_tegra114_disable()
1568 	u32 val, val_iddq;  in tegra_clk_register_pllxc()  local
1588 	val = readl_relaxed(clk_base + pll_params->base_reg);  in tegra_clk_register_pllxc()
1591 	if (val & PLL_BASE_ENABLE)  in tegra_clk_register_pllxc()
1617 	u32 val;  in tegra_clk_register_pllre()  local
1631 	val = pll_readl_base(pll);  in tegra_clk_register_pllre()
1632 	if (val & PLL_BASE_ENABLE)  in tegra_clk_register_pllre()
1633 		WARN_ON(val & pll_params->iddq_bit_idx);  in tegra_clk_register_pllre()
1638 		val = m << divm_shift(pll);  in tegra_clk_register_pllre()
1639 		val |= (pll_params->vco_min / parent_rate) << divn_shift(pll);  in tegra_clk_register_pllre()
1640 		pll_writel_base(val, pll);  in tegra_clk_register_pllre()
1645 	val = pll_readl_misc(pll);  in tegra_clk_register_pllre()
1646 	val &= ~BIT(29);  in tegra_clk_register_pllre()
1647 	pll_writel_misc(val, pll);  in tegra_clk_register_pllre()
1778 	u32 val, val_aux;  in tegra_clk_register_plle_tegra114()  local
1787 	val = pll_readl_base(pll);  in tegra_clk_register_plle_tegra114()
1790 	if (val & PLL_BASE_ENABLE) {  in tegra_clk_register_plle_tegra114()
1829 	u32 val;  in tegra_clk_register_pllss()  local
1847 	val = pll_readl_base(pll);  in tegra_clk_register_pllss()
1848 	val &= ~PLLSS_REF_SRC_SEL_MASK;  in tegra_clk_register_pllss()
1849 	pll_writel_base(val, pll);  in tegra_clk_register_pllss()
1876 	val = pll_readl_base(pll);  in tegra_clk_register_pllss()
1877 	if (val & PLL_BASE_ENABLE) {  in tegra_clk_register_pllss()
1878 		if (val & BIT(pll_params->iddq_bit_idx)) {  in tegra_clk_register_pllss()
1884 		val |= BIT(pll_params->iddq_bit_idx);  in tegra_clk_register_pllss()
1886 	val &= ~PLLSS_LOCK_OVERRIDE;  in tegra_clk_register_pllss()
1887 	pll_writel_base(val, pll);  in tegra_clk_register_pllss()