Lines Matching refs:writel_relaxed
997 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG2); in tegra114_utmi_param_configure()
1015 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
1022 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1027 writel_relaxed(reg, clk_base + UTMIP_PLL_CFG1); in tegra114_utmi_param_configure()
1036 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1043 writel_relaxed(reg, clk_base + UTMIPLL_HW_PWRDN_CFG0); in tegra114_utmi_param_configure()
1352 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); in tegra114_clock_tune_cpu_trimmers_high()
1379 writel_relaxed(select, clk_base + CPU_FINETRIM_SELECT); in tegra114_clock_tune_cpu_trimmers_low()
1401 writel_relaxed(r, clk_base + CPU_FINETRIM_R); in tegra114_clock_tune_cpu_trimmers_init()
1410 writel_relaxed(dr, clk_base + CPU_FINETRIM_DR); in tegra114_clock_tune_cpu_trimmers_init()
1427 writel_relaxed(v, clk_base + RST_DFLL_DVCO); in tegra114_clock_assert_dfll_dvco_reset()
1444 writel_relaxed(v, clk_base + RST_DFLL_DVCO); in tegra114_clock_deassert_dfll_dvco_reset()