Lines Matching refs:clks

167 static struct clk **clks;  variable
643 clks[TEGRA20_CLK_PLL_C] = clk; in tegra20_pll_init()
652 clks[TEGRA20_CLK_PLL_C_OUT1] = clk; in tegra20_pll_init()
658 clks[TEGRA20_CLK_PLL_M] = clk; in tegra20_pll_init()
667 clks[TEGRA20_CLK_PLL_M_OUT1] = clk; in tegra20_pll_init()
672 clks[TEGRA20_CLK_PLL_X] = clk; in tegra20_pll_init()
677 clks[TEGRA20_CLK_PLL_U] = clk; in tegra20_pll_init()
682 clks[TEGRA20_CLK_PLL_D] = clk; in tegra20_pll_init()
687 clks[TEGRA20_CLK_PLL_D_OUT0] = clk; in tegra20_pll_init()
692 clks[TEGRA20_CLK_PLL_A] = clk; in tegra20_pll_init()
701 clks[TEGRA20_CLK_PLL_A_OUT0] = clk; in tegra20_pll_init()
706 clks[TEGRA20_CLK_PLL_E] = clk; in tegra20_pll_init()
724 clks[TEGRA20_CLK_CCLK] = clk; in tegra20_super_clk_init()
730 clks[TEGRA20_CLK_SCLK] = clk; in tegra20_super_clk_init()
734 clks[TEGRA20_CLK_TWD] = clk; in tegra20_super_clk_init()
753 clks[TEGRA20_CLK_AUDIO] = clk; in tegra20_audio_clk_init()
762 clks[TEGRA20_CLK_AUDIO_2X] = clk; in tegra20_audio_clk_init()
812 clks[TEGRA20_CLK_AC97] = clk; in tegra20_periph_clk_init()
817 clks[TEGRA20_CLK_APBDMA] = clk; in tegra20_periph_clk_init()
827 clks[TEGRA20_CLK_EMC] = clk; in tegra20_periph_clk_init()
831 clks[TEGRA20_CLK_MC] = clk; in tegra20_periph_clk_init()
837 clks[TEGRA20_CLK_DSI] = clk; in tegra20_periph_clk_init()
842 clks[TEGRA20_CLK_PEX] = clk; in tegra20_periph_clk_init()
849 clks[TEGRA20_CLK_CDEV1] = clk; in tegra20_periph_clk_init()
856 clks[TEGRA20_CLK_CDEV2] = clk; in tegra20_periph_clk_init()
863 clks[data->clk_id] = clk; in tegra20_periph_clk_init()
872 clks[data->clk_id] = clk; in tegra20_periph_clk_init()
889 clks[TEGRA20_CLK_CLK_M] = clk; in tegra20_osc_clk_init()
895 clks[TEGRA20_CLK_PLL_REF] = clk; in tegra20_osc_clk_init()
1071 tegra_init_from_table(init_table, clks, TEGRA20_CLK_CLK_MAX); in tegra20_clock_apply_init_table()
1114 clks = tegra_clk_init(clk_base, TEGRA20_CLK_CLK_MAX, in tegra20_clock_init()
1116 if (!clks) in tegra20_clock_init()
1128 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA20_CLK_CLK_MAX); in tegra20_clock_init()