209 static struct clk **clks;  variable
930 	clks[TEGRA30_CLK_PLL_C] = clk;  in tegra30_pll_init()
939 	clks[TEGRA30_CLK_PLL_C_OUT1] = clk;  in tegra30_pll_init()
945 	clks[TEGRA30_CLK_PLL_M] = clk;  in tegra30_pll_init()
954 	clks[TEGRA30_CLK_PLL_M_OUT1] = clk;  in tegra30_pll_init()
959 	clks[TEGRA30_CLK_PLL_X] = clk;  in tegra30_pll_init()
964 	clks[TEGRA30_CLK_PLL_X_OUT0] = clk;  in tegra30_pll_init()
969 	clks[TEGRA30_CLK_PLL_U] = clk;  in tegra30_pll_init()
976 	clks[TEGRA30_CLK_PLL_D] = clk;  in tegra30_pll_init()
981 	clks[TEGRA30_CLK_PLL_D_OUT0] = clk;  in tegra30_pll_init()
986 	clks[TEGRA30_CLK_PLL_D2] = clk;  in tegra30_pll_init()
991 	clks[TEGRA30_CLK_PLL_D2_OUT0] = clk;  in tegra30_pll_init()
1000 	clks[TEGRA30_CLK_PLL_E] = clk;  in tegra30_pll_init()
1051 	clks[TEGRA30_CLK_CCLK_G] = clk;  in tegra30_super_clk_init()
1087 	clks[TEGRA30_CLK_CCLK_LP] = clk;  in tegra30_super_clk_init()
1095 	clks[TEGRA30_CLK_SCLK] = clk;  in tegra30_super_clk_init()
1100 	clks[TEGRA30_CLK_TWD] = clk;  in tegra30_super_clk_init()
1144 	clks[TEGRA30_CLK_DSIA] = clk;  in tegra30_periph_clk_init()
1149 	clks[TEGRA30_CLK_PCIE] = clk;  in tegra30_periph_clk_init()
1154 	clks[TEGRA30_CLK_AFI] = clk;  in tegra30_periph_clk_init()
1164 	clks[TEGRA30_CLK_EMC] = clk;  in tegra30_periph_clk_init()
1168 	clks[TEGRA30_CLK_MC] = clk;  in tegra30_periph_clk_init()
1173 	clks[TEGRA30_CLK_CML0] = clk;  in tegra30_periph_clk_init()
1178 	clks[TEGRA30_CLK_CML1] = clk;  in tegra30_periph_clk_init()
1185 		clks[data->clk_id] = clk;  in tegra30_periph_clk_init()
1194 		clks[data->clk_id] = clk;  in tegra30_periph_clk_init()
1381 	tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);  in tegra30_clock_apply_init_table()
1431 	clks = tegra_clk_init(clk_base, TEGRA30_CLK_CLK_MAX,  in tegra30_clock_init()
1433 	if (!clks)  in tegra30_clock_init()
1449 	tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);  in tegra30_clock_init()