105 	val = ti_clk_ll_ops->clk_readl(divider->reg) >> divider->shift;  in ti_clk_divider_recalc_rate()
235 		val = div_mask(divider) << (divider->shift + 16);  in ti_clk_divider_set_rate()
238 		val &= ~(div_mask(divider) << divider->shift);  in ti_clk_divider_set_rate()
240 	val |= value << divider->shift;  in ti_clk_divider_set_rate()
258 				     u8 shift, u8 width, u8 clk_divider_flags,  in _register_divider()  argument
267 		if (width + shift > 16) {  in _register_divider()
288 	div->shift = shift;  in _register_divider()
386 	div->shift = setup->bit_shift;  in ti_clk_build_component_div()
528 	u32 *flags, u8 *div_flags, u8 *width, u8 *shift)  in ti_clk_divider_populate()  argument
537 		*shift = val;  in ti_clk_divider_populate()
539 		*shift = 0;  in ti_clk_divider_populate()
576 	u8 shift = 0;  in of_ti_divider_clk_setup()  local
583 				    &clk_divider_flags, &width, &shift))  in of_ti_divider_clk_setup()
587 				shift, width, clk_divider_flags, table,  in of_ti_divider_clk_setup()
611 				    &div->flags, &div->width, &div->shift) < 0)  in of_ti_composite_divider_clk_setup()