Lines Matching refs:BIT
219 BIT(0), 0); in u8500_clk_init()
223 BIT(1), 0); in u8500_clk_init()
227 BIT(2), 0); in u8500_clk_init()
231 BIT(3), 0); in u8500_clk_init()
236 BIT(4), 0); in u8500_clk_init()
241 BIT(5), 0); in u8500_clk_init()
245 BIT(6), 0); in u8500_clk_init()
249 BIT(7), 0); in u8500_clk_init()
253 BIT(8), 0); in u8500_clk_init()
257 BIT(9), 0); in u8500_clk_init()
263 BIT(10), 0); in u8500_clk_init()
267 BIT(11), 0); in u8500_clk_init()
272 BIT(0), 0); in u8500_clk_init()
276 BIT(1), 0); in u8500_clk_init()
280 BIT(2), 0); in u8500_clk_init()
284 BIT(3), 0); in u8500_clk_init()
288 BIT(4), 0); in u8500_clk_init()
292 BIT(5), 0); in u8500_clk_init()
297 BIT(6), 0); in u8500_clk_init()
301 BIT(7), 0); in u8500_clk_init()
305 BIT(8), 0); in u8500_clk_init()
309 BIT(9), 0); in u8500_clk_init()
313 BIT(10), 0); in u8500_clk_init()
317 BIT(11), 0); in u8500_clk_init()
323 BIT(12), 0); in u8500_clk_init()
326 BIT(0), 0); in u8500_clk_init()
331 BIT(1), 0); in u8500_clk_init()
335 BIT(2), 0); in u8500_clk_init()
339 BIT(3), 0); in u8500_clk_init()
343 BIT(4), 0); in u8500_clk_init()
347 BIT(5), 0); in u8500_clk_init()
352 BIT(6), 0); in u8500_clk_init()
356 BIT(7), 0); in u8500_clk_init()
360 BIT(8), 0); in u8500_clk_init()
368 BIT(0), 0); in u8500_clk_init()
372 BIT(1), 0); in u8500_clk_init()
377 BIT(0), 0); in u8500_clk_init()
381 BIT(1), 0); in u8500_clk_init()
386 BIT(2), 0); in u8500_clk_init()
390 BIT(3), 0); in u8500_clk_init()
394 BIT(4), 0); in u8500_clk_init()
398 BIT(5), 0); in u8500_clk_init()
402 BIT(6), 0); in u8500_clk_init()
406 BIT(7), 0); in u8500_clk_init()
419 clkrst1_base, BIT(0), CLK_SET_RATE_GATE); in u8500_clk_init()
423 clkrst1_base, BIT(1), CLK_SET_RATE_GATE); in u8500_clk_init()
427 clkrst1_base, BIT(2), CLK_SET_RATE_GATE); in u8500_clk_init()
431 clkrst1_base, BIT(3), CLK_SET_RATE_GATE); in u8500_clk_init()
436 clkrst1_base, BIT(4), CLK_SET_RATE_GATE); in u8500_clk_init()
441 clkrst1_base, BIT(5), CLK_SET_RATE_GATE); in u8500_clk_init()
445 clkrst1_base, BIT(6), CLK_SET_RATE_GATE); in u8500_clk_init()
449 clkrst1_base, BIT(8), CLK_SET_RATE_GATE); in u8500_clk_init()
453 clkrst1_base, BIT(9), CLK_SET_RATE_GATE); in u8500_clk_init()
457 clkrst1_base, BIT(10), CLK_SET_RATE_GATE); in u8500_clk_init()
463 clkrst2_base, BIT(0), CLK_SET_RATE_GATE); in u8500_clk_init()
467 clkrst2_base, BIT(2), CLK_SET_RATE_GATE); in u8500_clk_init()
471 clkrst2_base, BIT(3), CLK_SET_RATE_GATE); in u8500_clk_init()
476 clkrst2_base, BIT(4), CLK_SET_RATE_GATE); in u8500_clk_init()
480 clkrst2_base, BIT(5), CLK_SET_RATE_GATE); in u8500_clk_init()
485 clkrst2_base, BIT(6), in u8500_clk_init()
488 clkrst2_base, BIT(7), in u8500_clk_init()
493 clkrst3_base, BIT(1), CLK_SET_RATE_GATE); in u8500_clk_init()
497 clkrst3_base, BIT(2), CLK_SET_RATE_GATE); in u8500_clk_init()
501 clkrst3_base, BIT(3), CLK_SET_RATE_GATE); in u8500_clk_init()
505 clkrst3_base, BIT(4), CLK_SET_RATE_GATE); in u8500_clk_init()
509 clkrst3_base, BIT(5), CLK_SET_RATE_GATE); in u8500_clk_init()
514 clkrst3_base, BIT(6), CLK_SET_RATE_GATE); in u8500_clk_init()
518 clkrst3_base, BIT(7), CLK_SET_RATE_GATE); in u8500_clk_init()
523 clkrst6_base, BIT(0), CLK_SET_RATE_GATE); in u8500_clk_init()