Lines Matching refs:BIT

250 				BIT(0), 0);  in u8500_of_clk_init()
254 BIT(1), 0); in u8500_of_clk_init()
258 BIT(2), 0); in u8500_of_clk_init()
262 BIT(3), 0); in u8500_of_clk_init()
266 BIT(4), 0); in u8500_of_clk_init()
270 BIT(5), 0); in u8500_of_clk_init()
274 BIT(6), 0); in u8500_of_clk_init()
278 BIT(7), 0); in u8500_of_clk_init()
282 BIT(8), 0); in u8500_of_clk_init()
286 BIT(9), 0); in u8500_of_clk_init()
290 BIT(10), 0); in u8500_of_clk_init()
294 BIT(11), 0); in u8500_of_clk_init()
298 BIT(0), 0); in u8500_of_clk_init()
302 BIT(1), 0); in u8500_of_clk_init()
306 BIT(2), 0); in u8500_of_clk_init()
310 BIT(3), 0); in u8500_of_clk_init()
314 BIT(4), 0); in u8500_of_clk_init()
318 BIT(5), 0); in u8500_of_clk_init()
322 BIT(6), 0); in u8500_of_clk_init()
326 BIT(7), 0); in u8500_of_clk_init()
330 BIT(8), 0); in u8500_of_clk_init()
334 BIT(9), 0); in u8500_of_clk_init()
338 BIT(10), 0); in u8500_of_clk_init()
342 BIT(11), 0); in u8500_of_clk_init()
346 BIT(12), 0); in u8500_of_clk_init()
350 BIT(0), 0); in u8500_of_clk_init()
354 BIT(1), 0); in u8500_of_clk_init()
358 BIT(2), 0); in u8500_of_clk_init()
362 BIT(3), 0); in u8500_of_clk_init()
366 BIT(4), 0); in u8500_of_clk_init()
370 BIT(5), 0); in u8500_of_clk_init()
374 BIT(6), 0); in u8500_of_clk_init()
378 BIT(7), 0); in u8500_of_clk_init()
382 BIT(8), 0); in u8500_of_clk_init()
386 BIT(0), 0); in u8500_of_clk_init()
390 BIT(1), 0); in u8500_of_clk_init()
394 BIT(0), 0); in u8500_of_clk_init()
398 BIT(1), 0); in u8500_of_clk_init()
402 BIT(2), 0); in u8500_of_clk_init()
406 BIT(3), 0); in u8500_of_clk_init()
410 BIT(4), 0); in u8500_of_clk_init()
414 BIT(5), 0); in u8500_of_clk_init()
418 BIT(6), 0); in u8500_of_clk_init()
422 BIT(7), 0); in u8500_of_clk_init()
435 clkrst1_base, BIT(0), CLK_SET_RATE_GATE); in u8500_of_clk_init()
439 clkrst1_base, BIT(1), CLK_SET_RATE_GATE); in u8500_of_clk_init()
443 clkrst1_base, BIT(2), CLK_SET_RATE_GATE); in u8500_of_clk_init()
447 clkrst1_base, BIT(3), CLK_SET_RATE_GATE); in u8500_of_clk_init()
451 clkrst1_base, BIT(4), CLK_SET_RATE_GATE); in u8500_of_clk_init()
455 clkrst1_base, BIT(5), CLK_SET_RATE_GATE); in u8500_of_clk_init()
459 clkrst1_base, BIT(6), CLK_SET_RATE_GATE); in u8500_of_clk_init()
463 clkrst1_base, BIT(8), CLK_SET_RATE_GATE); in u8500_of_clk_init()
467 clkrst1_base, BIT(9), CLK_SET_RATE_GATE); in u8500_of_clk_init()
471 clkrst1_base, BIT(10), CLK_SET_RATE_GATE); in u8500_of_clk_init()
476 clkrst2_base, BIT(0), CLK_SET_RATE_GATE); in u8500_of_clk_init()
480 clkrst2_base, BIT(2), CLK_SET_RATE_GATE); in u8500_of_clk_init()
484 clkrst2_base, BIT(3), CLK_SET_RATE_GATE); in u8500_of_clk_init()
488 clkrst2_base, BIT(4), CLK_SET_RATE_GATE); in u8500_of_clk_init()
492 clkrst2_base, BIT(5), CLK_SET_RATE_GATE); in u8500_of_clk_init()
497 clkrst2_base, BIT(6), in u8500_of_clk_init()
502 clkrst2_base, BIT(7), in u8500_of_clk_init()
508 clkrst3_base, BIT(1), CLK_SET_RATE_GATE); in u8500_of_clk_init()
512 clkrst3_base, BIT(2), CLK_SET_RATE_GATE); in u8500_of_clk_init()
516 clkrst3_base, BIT(3), CLK_SET_RATE_GATE); in u8500_of_clk_init()
520 clkrst3_base, BIT(4), CLK_SET_RATE_GATE); in u8500_of_clk_init()
524 clkrst3_base, BIT(5), CLK_SET_RATE_GATE); in u8500_of_clk_init()
528 clkrst3_base, BIT(6), CLK_SET_RATE_GATE); in u8500_of_clk_init()
532 clkrst3_base, BIT(7), CLK_SET_RATE_GATE); in u8500_of_clk_init()
537 clkrst6_base, BIT(0), CLK_SET_RATE_GATE); in u8500_of_clk_init()