93 	struct sh_cmt_device *cmt;  member
242 		return ch->cmt->info->read_control(ch->iostart, 0);  in sh_cmt_read_cmstr()
244 		return ch->cmt->info->read_control(ch->cmt->mapbase, 0);  in sh_cmt_read_cmstr()
251 		ch->cmt->info->write_control(ch->iostart, 0, value);  in sh_cmt_write_cmstr()
253 		ch->cmt->info->write_control(ch->cmt->mapbase, 0, value);  in sh_cmt_write_cmstr()
258 	return ch->cmt->info->read_control(ch->ioctrl, CMCSR);  in sh_cmt_read_cmcsr()
264 	ch->cmt->info->write_control(ch->ioctrl, CMCSR, value);  in sh_cmt_write_cmcsr()
269 	return ch->cmt->info->read_count(ch->ioctrl, CMCNT);  in sh_cmt_read_cmcnt()
275 	ch->cmt->info->write_count(ch->ioctrl, CMCNT, value);  in sh_cmt_write_cmcnt()
281 	ch->cmt->info->write_count(ch->ioctrl, CMCOR, value);  in sh_cmt_write_cmcor()
290 	o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;  in sh_cmt_get_counter()
298 		o1 = sh_cmt_read_cmcsr(ch) & ch->cmt->info->overflow_bit;  in sh_cmt_get_counter()
311 	raw_spin_lock_irqsave(&ch->cmt->lock, flags);  in sh_cmt_start_stop_ch()
320 	raw_spin_unlock_irqrestore(&ch->cmt->lock, flags);  in sh_cmt_start_stop_ch()
327 	pm_runtime_get_sync(&ch->cmt->pdev->dev);  in sh_cmt_enable()
328 	dev_pm_syscore_device(&ch->cmt->pdev->dev, true);  in sh_cmt_enable()
331 	ret = clk_enable(ch->cmt->clk);  in sh_cmt_enable()
333 		dev_err(&ch->cmt->pdev->dev, "ch%u: cannot enable clock\n",  in sh_cmt_enable()
342 	if (ch->cmt->info->width == 16) {  in sh_cmt_enable()
343 		*rate = clk_get_rate(ch->cmt->clk) / 512;  in sh_cmt_enable()
347 		*rate = clk_get_rate(ch->cmt->clk) / 8;  in sh_cmt_enable()
375 		dev_err(&ch->cmt->pdev->dev, "ch%u: cannot clear CMCNT\n",  in sh_cmt_enable()
386 	clk_disable(ch->cmt->clk);  in sh_cmt_enable()
401 	clk_disable(ch->cmt->clk);  in sh_cmt_disable()
403 	dev_pm_syscore_device(&ch->cmt->pdev->dev, false);  in sh_cmt_disable()
404 	pm_runtime_put(&ch->cmt->pdev->dev);  in sh_cmt_disable()
494 			dev_warn(&ch->cmt->pdev->dev, "ch%u: too long delay\n",  in sh_cmt_clock_event_program_verify()
503 		dev_warn(&ch->cmt->pdev->dev, "ch%u: delta out of range\n",  in __sh_cmt_set_next()
525 			   ch->cmt->info->clear_bits);  in sh_cmt_interrupt()
665 	pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);  in sh_cmt_clocksource_suspend()
672 	pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);  in sh_cmt_clocksource_resume()
691 	dev_info(&ch->cmt->pdev->dev, "ch%u: used as clock source\n",  in sh_cmt_register_clocksource()
740 		dev_info(&ch->cmt->pdev->dev,  in sh_cmt_clock_event_mode()
745 		dev_info(&ch->cmt->pdev->dev,  in sh_cmt_clock_event_mode()
776 	pm_genpd_syscore_poweroff(&ch->cmt->pdev->dev);  in sh_cmt_clock_event_suspend()
777 	clk_unprepare(ch->cmt->clk);  in sh_cmt_clock_event_suspend()
784 	clk_prepare(ch->cmt->clk);  in sh_cmt_clock_event_resume()
785 	pm_genpd_syscore_poweron(&ch->cmt->pdev->dev);  in sh_cmt_clock_event_resume()
795 	irq = platform_get_irq(ch->cmt->pdev, ch->index);  in sh_cmt_register_clockevent()
797 		dev_err(&ch->cmt->pdev->dev, "ch%u: failed to get irq\n",  in sh_cmt_register_clockevent()
804 			  dev_name(&ch->cmt->pdev->dev), ch);  in sh_cmt_register_clockevent()
806 		dev_err(&ch->cmt->pdev->dev, "ch%u: failed to request irq %d\n",  in sh_cmt_register_clockevent()
821 	dev_info(&ch->cmt->pdev->dev, "ch%u: used for clock events\n",  in sh_cmt_register_clockevent()
834 		ch->cmt->has_clockevent = true;  in sh_cmt_register()
841 		ch->cmt->has_clocksource = true;  in sh_cmt_register()
850 				bool clocksource, struct sh_cmt_device *cmt)  in sh_cmt_setup_channel()  argument
858 	ch->cmt = cmt;  in sh_cmt_setup_channel()
867 	switch (cmt->info->model) {  in sh_cmt_setup_channel()
869 		ch->ioctrl = cmt->mapbase + 2 + ch->hwidx * 6;  in sh_cmt_setup_channel()
873 		ch->ioctrl = cmt->mapbase + 0x10 + ch->hwidx * 0x10;  in sh_cmt_setup_channel()
880 		ch->ioctrl = cmt->mapbase + 0x40;  in sh_cmt_setup_channel()
883 		ch->iostart = cmt->mapbase + ch->hwidx * 0x100;  in sh_cmt_setup_channel()
888 	if (cmt->info->width == (sizeof(ch->max_match_value) * 8))  in sh_cmt_setup_channel()
891 		ch->max_match_value = (1 << cmt->info->width) - 1;  in sh_cmt_setup_channel()
896 	ch->timer_bit = cmt->info->model == SH_CMT_48BIT_GEN2 ? 0 : ch->hwidx;  in sh_cmt_setup_channel()
898 	ret = sh_cmt_register(ch, dev_name(&cmt->pdev->dev),  in sh_cmt_setup_channel()
901 		dev_err(&cmt->pdev->dev, "ch%u: registration failed\n",  in sh_cmt_setup_channel()
910 static int sh_cmt_map_memory(struct sh_cmt_device *cmt)  in sh_cmt_map_memory()  argument
914 	mem = platform_get_resource(cmt->pdev, IORESOURCE_MEM, 0);  in sh_cmt_map_memory()
916 		dev_err(&cmt->pdev->dev, "failed to get I/O memory\n");  in sh_cmt_map_memory()
920 	cmt->mapbase = ioremap_nocache(mem->start, resource_size(mem));  in sh_cmt_map_memory()
921 	if (cmt->mapbase == NULL) {  in sh_cmt_map_memory()
922 		dev_err(&cmt->pdev->dev, "failed to remap I/O memory\n");  in sh_cmt_map_memory()
948 static int sh_cmt_parse_dt(struct sh_cmt_device *cmt)  in sh_cmt_parse_dt()  argument
950 	struct device_node *np = cmt->pdev->dev.of_node;  in sh_cmt_parse_dt()
953 				    &cmt->hw_channels);  in sh_cmt_parse_dt()
956 static int sh_cmt_setup(struct sh_cmt_device *cmt, struct platform_device *pdev)  in sh_cmt_setup()  argument
962 	memset(cmt, 0, sizeof(*cmt));  in sh_cmt_setup()
963 	cmt->pdev = pdev;  in sh_cmt_setup()
964 	raw_spin_lock_init(&cmt->lock);  in sh_cmt_setup()
970 		cmt->info = id->data;  in sh_cmt_setup()
972 		ret = sh_cmt_parse_dt(cmt);  in sh_cmt_setup()
979 		cmt->info = (const struct sh_cmt_info *)id->driver_data;  in sh_cmt_setup()
980 		cmt->hw_channels = cfg->channels_mask;  in sh_cmt_setup()
982 		dev_err(&cmt->pdev->dev, "missing platform data\n");  in sh_cmt_setup()
987 	cmt->clk = clk_get(&cmt->pdev->dev, "fck");  in sh_cmt_setup()
988 	if (IS_ERR(cmt->clk)) {  in sh_cmt_setup()
989 		dev_err(&cmt->pdev->dev, "cannot get clock\n");  in sh_cmt_setup()
990 		return PTR_ERR(cmt->clk);  in sh_cmt_setup()
993 	ret = clk_prepare(cmt->clk);  in sh_cmt_setup()
998 	ret = sh_cmt_map_memory(cmt);  in sh_cmt_setup()
1003 	cmt->num_channels = hweight8(cmt->hw_channels);  in sh_cmt_setup()
1004 	cmt->channels = kzalloc(cmt->num_channels * sizeof(*cmt->channels),  in sh_cmt_setup()
1006 	if (cmt->channels == NULL) {  in sh_cmt_setup()
1015 	for (i = 0, mask = cmt->hw_channels; i < cmt->num_channels; ++i) {  in sh_cmt_setup()
1017 		bool clocksource = i == 1 || cmt->num_channels == 1;  in sh_cmt_setup()
1020 		ret = sh_cmt_setup_channel(&cmt->channels[i], i, hwidx,  in sh_cmt_setup()
1021 					   clockevent, clocksource, cmt);  in sh_cmt_setup()
1028 	platform_set_drvdata(pdev, cmt);  in sh_cmt_setup()
1033 	kfree(cmt->channels);  in sh_cmt_setup()
1034 	iounmap(cmt->mapbase);  in sh_cmt_setup()
1036 	clk_unprepare(cmt->clk);  in sh_cmt_setup()
1038 	clk_put(cmt->clk);  in sh_cmt_setup()
1044 	struct sh_cmt_device *cmt = platform_get_drvdata(pdev);  in sh_cmt_probe()  local
1052 	if (cmt) {  in sh_cmt_probe()
1057 	cmt = kzalloc(sizeof(*cmt), GFP_KERNEL);  in sh_cmt_probe()
1058 	if (cmt == NULL)  in sh_cmt_probe()
1061 	ret = sh_cmt_setup(cmt, pdev);  in sh_cmt_probe()
1063 		kfree(cmt);  in sh_cmt_probe()
1071 	if (cmt->has_clockevent || cmt->has_clocksource)  in sh_cmt_probe()