42 static void __iomem *tcaddr;  variable
51 		upper = __raw_readl(tcaddr + ATMEL_TC_REG(1, CV));  in tc_get_cycles()
52 		lower = __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));  in tc_get_cycles()
53 	} while (upper != __raw_readl(tcaddr + ATMEL_TC_REG(1, CV)));  in tc_get_cycles()
61 	return __raw_readl(tcaddr + ATMEL_TC_REG(0, CV));  in tc_get_cycles32()
118 		__raw_writel((32768 + HZ/2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));  in tc_mode()
147 	__raw_writel(delta, tcaddr + ATMEL_TC_REG(2, RC));  in tc_next_event()
151 			tcaddr + ATMEL_TC_REG(2, CCR));  in tc_next_event()
229 			tcaddr + ATMEL_TC_REG(0, CMR));  in tcb_setup_dual_chan()
230 	__raw_writel(0x0000, tcaddr + ATMEL_TC_REG(0, RA));  in tcb_setup_dual_chan()
231 	__raw_writel(0x8000, tcaddr + ATMEL_TC_REG(0, RC));  in tcb_setup_dual_chan()
232 	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */  in tcb_setup_dual_chan()
233 	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));  in tcb_setup_dual_chan()
239 			tcaddr + ATMEL_TC_REG(1, CMR));  in tcb_setup_dual_chan()
240 	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(1, IDR));	/* no irqs */  in tcb_setup_dual_chan()
241 	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(1, CCR));  in tcb_setup_dual_chan()
244 	__raw_writel(ATMEL_TC_TC1XC1S_TIOA0, tcaddr + ATMEL_TC_BMR);  in tcb_setup_dual_chan()
246 	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);  in tcb_setup_dual_chan()
255 			tcaddr + ATMEL_TC_REG(0, CMR));  in tcb_setup_single_chan()
256 	__raw_writel(0xff, tcaddr + ATMEL_TC_REG(0, IDR));	/* no irqs */  in tcb_setup_single_chan()
257 	__raw_writel(ATMEL_TC_CLKEN, tcaddr + ATMEL_TC_REG(0, CCR));  in tcb_setup_single_chan()
260 	__raw_writel(ATMEL_TC_SYNC, tcaddr + ATMEL_TC_BCR);  in tcb_setup_single_chan()
282 	tcaddr = tc->regs;  in tcb_clksrc_init()