Lines Matching refs:cctl
189 u32 cctl; member
485 static inline u32 get_bytes_in_cctl(u32 cctl) in get_bytes_in_cctl() argument
488 u32 bytes = cctl & PL080_CONTROL_TRANSFER_SIZE_MASK; in get_bytes_in_cctl()
490 cctl &= PL080_CONTROL_SWIDTH_MASK; in get_bytes_in_cctl()
492 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { in get_bytes_in_cctl()
505 static inline u32 get_bytes_in_cctl_pl080s(u32 cctl, u32 cctl1) in get_bytes_in_cctl_pl080s() argument
510 cctl &= PL080_CONTROL_SWIDTH_MASK; in get_bytes_in_cctl_pl080s()
512 switch (cctl >> PL080_CONTROL_SWIDTH_SHIFT) { in get_bytes_in_cctl_pl080s()
757 static inline u32 pl08x_cctl_bits(u32 cctl, u8 srcwidth, u8 dstwidth, in pl08x_cctl_bits() argument
760 u32 retbits = cctl; in pl08x_cctl_bits()
821 struct pl08x_bus_data **mbus, struct pl08x_bus_data **sbus, u32 cctl) in pl08x_choose_master_bus() argument
823 if (!(cctl & PL080_CONTROL_DST_INCR)) { in pl08x_choose_master_bus()
826 } else if (!(cctl & PL080_CONTROL_SRC_INCR)) { in pl08x_choose_master_bus()
845 int num_llis, int len, u32 cctl, u32 cctl2) in pl08x_fill_lli_for_desc() argument
860 llis_va[PL080_LLI_CCTL] = cctl; in pl08x_fill_lli_for_desc()
864 if (cctl & PL080_CONTROL_SRC_INCR) in pl08x_fill_lli_for_desc()
866 if (cctl & PL080_CONTROL_DST_INCR) in pl08x_fill_lli_for_desc()
875 struct pl08x_lli_build_data *bd, u32 *cctl, u32 len, in prep_byte_width_lli() argument
878 *cctl = pl08x_cctl_bits(*cctl, 1, 1, len); in prep_byte_width_lli()
879 pl08x_fill_lli_for_desc(pl08x, bd, num_llis, len, *cctl, len); in prep_byte_width_lli()
932 u32 cctl, early_bytes = 0; in pl08x_fill_llis_for_desc() local
945 cctl = txd->cctl; in pl08x_fill_llis_for_desc()
949 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_SWIDTH_MASK) >> in pl08x_fill_llis_for_desc()
954 pl08x_get_bytes_for_cctl((cctl & PL080_CONTROL_DWIDTH_MASK) >> in pl08x_fill_llis_for_desc()
959 cctl = txd->cctl; in pl08x_fill_llis_for_desc()
967 pl08x_choose_master_bus(&bd, &mbus, &sbus, cctl); in pl08x_fill_llis_for_desc()
972 cctl & PL080_CONTROL_SRC_INCR ? "+" : "", in pl08x_fill_llis_for_desc()
975 cctl & PL080_CONTROL_DST_INCR ? "+" : "", in pl08x_fill_llis_for_desc()
1022 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, in pl08x_fill_llis_for_desc()
1025 0, cctl, 0); in pl08x_fill_llis_for_desc()
1047 prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes, in pl08x_fill_llis_for_desc()
1102 cctl = pl08x_cctl_bits(cctl, bd.srcbus.buswidth, in pl08x_fill_llis_for_desc()
1105 lli_len, cctl, tsize); in pl08x_fill_llis_for_desc()
1116 prep_byte_width_lli(pl08x, &bd, &cctl, in pl08x_fill_llis_for_desc()
1314 u32 cctl = 0; in pl08x_select_bus() local
1317 cctl |= PL080_CONTROL_DST_AHB2; in pl08x_select_bus()
1319 cctl |= PL080_CONTROL_SRC_AHB2; in pl08x_select_bus()
1321 return cctl; in pl08x_select_bus()
1324 static u32 pl08x_cctl(u32 cctl) in pl08x_cctl() argument
1326 cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 | in pl08x_cctl()
1331 return cctl | PL080_CONTROL_PROT_SYS; in pl08x_cctl()
1362 u32 width, burst, cctl = 0; in pl08x_get_cctl() local
1368 cctl |= width << PL080_CONTROL_SWIDTH_SHIFT; in pl08x_get_cctl()
1369 cctl |= width << PL080_CONTROL_DWIDTH_SHIFT; in pl08x_get_cctl()
1380 cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT; in pl08x_get_cctl()
1381 cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT; in pl08x_get_cctl()
1383 return pl08x_cctl(cctl); in pl08x_get_cctl()
1452 txd->cctl = pl08x->pd->memcpy_channel.cctl_memcpy & in pl08x_prep_dma_memcpy()
1456 txd->cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR; in pl08x_prep_dma_memcpy()
1459 txd->cctl |= pl08x_select_bus(pl08x->mem_buses, in pl08x_prep_dma_memcpy()
1482 u32 maxburst, cctl; in pl08x_init_txd() local
1496 cctl = PL080_CONTROL_SRC_INCR; in pl08x_init_txd()
1503 cctl = PL080_CONTROL_DST_INCR; in pl08x_init_txd()
1516 cctl |= pl08x_get_cctl(plchan, addr_width, maxburst); in pl08x_init_txd()
1517 if (cctl == ~0) { in pl08x_init_txd()
1524 txd->cctl = cctl | pl08x_select_bus(src_buses, dst_buses); in pl08x_init_txd()
1646 txd->cctl |= PL080_CONTROL_TC_IRQ_EN; in pl08x_prep_dma_cyclic()