194 	struct tegra_dma	*tdma;  member
232 static inline void tdma_write(struct tegra_dma *tdma, u32 reg, u32 val)  in tdma_write()  argument
234 	writel(val, tdma->base_addr + reg);  in tdma_write()
237 static inline u32 tdma_read(struct tegra_dma *tdma, u32 reg)  in tdma_read()  argument
239 	return readl(tdma->base_addr + reg);  in tdma_read()
245 	writel(val, tdc->tdma->base_addr + tdc->chan_base_offset + reg);  in tdc_write()
250 	return readl(tdc->tdma->base_addr + tdc->chan_base_offset + reg);  in tdc_read()
361 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_global_pause()  local
363 	spin_lock(&tdma->global_lock);  in tegra_dma_global_pause()
364 	tdma_write(tdma, TEGRA_APBDMA_GENERAL, 0);  in tegra_dma_global_pause()
371 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_global_resume()  local
373 	tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);  in tegra_dma_global_resume()
374 	spin_unlock(&tdma->global_lock);  in tegra_dma_global_resume()
380 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_pause()  local
382 	if (tdma->chip_data->support_channel_pause) {  in tegra_dma_pause()
394 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_resume()  local
396 	if (tdma->chip_data->support_channel_pause) {  in tegra_dma_resume()
436 	if (tdc->tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_start()
477 	if (tdc->tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_configure_for_next()
754 	if (tdc->tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_terminate_all()
915 	if (tdc->tdma->chip_data->support_separate_wcount_reg)  in tegra_dma_prep_wcount()
985 				(len > tdc->tdma->chip_data->max_dma_count)) {  in tegra_dma_prep_slave_sg()
1085 			(len > tdc->tdma->chip_data->max_dma_count)) {  in tegra_dma_prep_dma_cyclic()
1173 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_alloc_chan_resources()  local
1178 	ret = clk_prepare_enable(tdma->dma_clk);  in tegra_dma_alloc_chan_resources()
1187 	struct tegra_dma *tdma = tdc->tdma;  in tegra_dma_free_chan_resources()  local
1224 	clk_disable_unprepare(tdma->dma_clk);  in tegra_dma_free_chan_resources()
1232 	struct tegra_dma *tdma = ofdma->of_dma_data;  in tegra_dma_of_xlate()  local
1236 	chan = dma_get_any_slave_channel(&tdma->dma_dev);  in tegra_dma_of_xlate()
1304 	struct tegra_dma *tdma;  in tegra_dma_probe()  local
1317 	tdma = devm_kzalloc(&pdev->dev, sizeof(*tdma) + cdata->nr_channels *  in tegra_dma_probe()
1319 	if (!tdma) {  in tegra_dma_probe()
1324 	tdma->dev = &pdev->dev;  in tegra_dma_probe()
1325 	tdma->chip_data = cdata;  in tegra_dma_probe()
1326 	platform_set_drvdata(pdev, tdma);  in tegra_dma_probe()
1329 	tdma->base_addr = devm_ioremap_resource(&pdev->dev, res);  in tegra_dma_probe()
1330 	if (IS_ERR(tdma->base_addr))  in tegra_dma_probe()
1331 		return PTR_ERR(tdma->base_addr);  in tegra_dma_probe()
1333 	tdma->dma_clk = devm_clk_get(&pdev->dev, NULL);  in tegra_dma_probe()
1334 	if (IS_ERR(tdma->dma_clk)) {  in tegra_dma_probe()
1336 		return PTR_ERR(tdma->dma_clk);  in tegra_dma_probe()
1339 	tdma->rst = devm_reset_control_get(&pdev->dev, "dma");  in tegra_dma_probe()
1340 	if (IS_ERR(tdma->rst)) {  in tegra_dma_probe()
1342 		return PTR_ERR(tdma->rst);  in tegra_dma_probe()
1345 	spin_lock_init(&tdma->global_lock);  in tegra_dma_probe()
1358 	ret = clk_prepare_enable(tdma->dma_clk);  in tegra_dma_probe()
1365 	reset_control_assert(tdma->rst);  in tegra_dma_probe()
1367 	reset_control_deassert(tdma->rst);  in tegra_dma_probe()
1370 	tdma_write(tdma, TEGRA_APBDMA_GENERAL, TEGRA_APBDMA_GENERAL_ENABLE);  in tegra_dma_probe()
1371 	tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);  in tegra_dma_probe()
1372 	tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);  in tegra_dma_probe()
1374 	clk_disable_unprepare(tdma->dma_clk);  in tegra_dma_probe()
1376 	INIT_LIST_HEAD(&tdma->dma_dev.channels);  in tegra_dma_probe()
1378 		struct tegra_dma_channel *tdc = &tdma->channels[i];  in tegra_dma_probe()
1400 		tdc->dma_chan.device = &tdma->dma_dev;  in tegra_dma_probe()
1403 				&tdma->dma_dev.channels);  in tegra_dma_probe()
1404 		tdc->tdma = tdma;  in tegra_dma_probe()
1417 	dma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);  in tegra_dma_probe()
1418 	dma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);  in tegra_dma_probe()
1419 	dma_cap_set(DMA_CYCLIC, tdma->dma_dev.cap_mask);  in tegra_dma_probe()
1421 	tdma->dma_dev.dev = &pdev->dev;  in tegra_dma_probe()
1422 	tdma->dma_dev.device_alloc_chan_resources =  in tegra_dma_probe()
1424 	tdma->dma_dev.device_free_chan_resources =  in tegra_dma_probe()
1426 	tdma->dma_dev.device_prep_slave_sg = tegra_dma_prep_slave_sg;  in tegra_dma_probe()
1427 	tdma->dma_dev.device_prep_dma_cyclic = tegra_dma_prep_dma_cyclic;  in tegra_dma_probe()
1428 	tdma->dma_dev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |  in tegra_dma_probe()
1432 	tdma->dma_dev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) |  in tegra_dma_probe()
1436 	tdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);  in tegra_dma_probe()
1442 	tdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;  in tegra_dma_probe()
1443 	tdma->dma_dev.device_config = tegra_dma_slave_config;  in tegra_dma_probe()
1444 	tdma->dma_dev.device_terminate_all = tegra_dma_terminate_all;  in tegra_dma_probe()
1445 	tdma->dma_dev.device_tx_status = tegra_dma_tx_status;  in tegra_dma_probe()
1446 	tdma->dma_dev.device_issue_pending = tegra_dma_issue_pending;  in tegra_dma_probe()
1448 	ret = dma_async_device_register(&tdma->dma_dev);  in tegra_dma_probe()
1456 					 tegra_dma_of_xlate, tdma);  in tegra_dma_probe()
1468 	dma_async_device_unregister(&tdma->dma_dev);  in tegra_dma_probe()
1471 		struct tegra_dma_channel *tdc = &tdma->channels[i];  in tegra_dma_probe()
1484 	struct tegra_dma *tdma = platform_get_drvdata(pdev);  in tegra_dma_remove()  local
1488 	dma_async_device_unregister(&tdma->dma_dev);  in tegra_dma_remove()
1490 	for (i = 0; i < tdma->chip_data->nr_channels; ++i) {  in tegra_dma_remove()
1491 		tdc = &tdma->channels[i];  in tegra_dma_remove()
1505 	struct tegra_dma *tdma = platform_get_drvdata(pdev);  in tegra_dma_runtime_suspend()  local
1507 	clk_disable_unprepare(tdma->dma_clk);  in tegra_dma_runtime_suspend()
1514 	struct tegra_dma *tdma = platform_get_drvdata(pdev);  in tegra_dma_runtime_resume()  local
1517 	ret = clk_prepare_enable(tdma->dma_clk);  in tegra_dma_runtime_resume()
1528 	struct tegra_dma *tdma = dev_get_drvdata(dev);  in tegra_dma_pm_suspend()  local
1537 	tdma->reg_gen = tdma_read(tdma, TEGRA_APBDMA_GENERAL);  in tegra_dma_pm_suspend()
1538 	for (i = 0; i < tdma->chip_data->nr_channels; i++) {  in tegra_dma_pm_suspend()
1539 		struct tegra_dma_channel *tdc = &tdma->channels[i];  in tegra_dma_pm_suspend()
1556 	struct tegra_dma *tdma = dev_get_drvdata(dev);  in tegra_dma_pm_resume()  local
1565 	tdma_write(tdma, TEGRA_APBDMA_GENERAL, tdma->reg_gen);  in tegra_dma_pm_resume()
1566 	tdma_write(tdma, TEGRA_APBDMA_CONTROL, 0);  in tegra_dma_pm_resume()
1567 	tdma_write(tdma, TEGRA_APBDMA_IRQ_MASK_SET, 0xFFFFFFFFul);  in tegra_dma_pm_resume()
1569 	for (i = 0; i < tdma->chip_data->nr_channels; i++) {  in tegra_dma_pm_resume()
1570 		struct tegra_dma_channel *tdc = &tdma->channels[i];  in tegra_dma_pm_resume()