Lines Matching refs:and

4 #	Licensed and distributed under the GPL
26 	  and:
48 	  levels are 0-4 (from low to high) and by default it is set to 2.
68 	  This is a simple debugfs interface to inject MCEs and test different
77 	  Some systems are able to detect and correct errors in main
79 	  detection and correction (EDAC - or commonly referred to ECC
98 	  It should be noticed that keeping both GHES and a hardware-driven
111 	  Support for error detection and correction of DRAM ECC errors on
118 	  Recent Opterons (Family 10h and later) provide for Memory Error
120 	  allows the operator/user to inject Uncorrectable and Correctable
130 	  In addition, there are two control files, inject_read and inject_write,
131 	  which trigger the DRAM ECC Read and Write respectively.
137 	  Support for error detection and correction on the AMD 76x
144 	  Support for error detection and correction on the Intel
145 	  E7205, E7500, E7501 and E7505 server chipsets.
148 	tristate "Intel e752x (e7520, e7525, e7320) and 3100"
151 	  Support for error detection and correction on the Intel
159 	  Support for error detection and correction on the Intel
166 	  Support for error detection and correction on the Intel
167 	  DP82785P and E7210 server chipsets.
173 	  Support for error detection and correction on the Intel
180 	  Support for error detection and correction on the Intel
181 	  3000 and 3010 server chipsets.
187 	  Support for error detection and correction on the Intel
188 	  3200 and 3210 server chipsets.
194 	  Support for error detection and correction on the Intel
201 	  Support for error detection and correction on the Intel
208 	  Support for error detection and correction the Intel
215 	  Support for error detection and correction the Intel
218 	  and Xeon 55xx processors.
224 	  Support for error detection and correction on the Intel
231 	  Support for error detection and correction on the Radisys
238 	  Support for error detection and correction the Intel
245 	  Support for error detection and correction the Intel
252 	  Support for error detection and correction the Intel
260 	  Support for error detection and correction the Intel
261 	  Sandy Bridge, Ivy Bridge and Haswell Integrated Memory Controllers.
267 	  Support for error detection and correction on the Freescale
274 	  Support for error detection and correction on the Marvell
275 	  MV64360 and MV64460 chipsets.
282 	  Support for error detection and correction on PA Semi
289 	  Support for error detection and correction on the
300 	  440SP, 440SPe, 460EX, 460GT and 460SX.
306 	  Support for error detection and correction on the
315 	  Support for error detection and correction on the
324 	  Support for error detection and correction on the
325 	  IBM CPC925 Bridge and Memory Controller, which is
334 	  Support for error detection and correction on the
341 	  Support for error detection and correction on the
348 	  Support for error detection and correction on the
355 	  Support for error detection and correction on the primary caches of
362 	  Support for error detection and correction on the
369 	  Support for error detection and correction on the
376 	  Support for error detection and correction on the
383 	  Support for error detection and correction on the
392 	  Support for error detection and correction on the Synopsys DDR