350 		csbase		= pvt->csels[dct].csbases[csrow];  in get_cs_base_and_mask()
351 		csmask		= pvt->csels[dct].csmasks[csrow];  in get_cs_base_and_mask()
362 		csbase          = pvt->csels[dct].csbases[csrow];  in get_cs_base_and_mask()
363 		csmask          = pvt->csels[dct].csmasks[csrow >> 1];  in get_cs_base_and_mask()
378 		csbase		= pvt->csels[dct].csbases[csrow];  in get_cs_base_and_mask()
379 		csmask		= pvt->csels[dct].csmasks[csrow >> 1];  in get_cs_base_and_mask()
400 	for (i = 0; i < pvt->csels[dct].b_cnt; i++)
403 	pvt->csels[dct].csbases[i]
406 	for (i = 0; i < pvt->csels[dct].m_cnt; i++)
695 		u32 dcsm = pvt->csels[chan].csmasks[0];  in debug_dump_dramcfg_low()
766 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;  in prep_chip_selects()
767 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;  in prep_chip_selects()
769 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;  in prep_chip_selects()
770 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;  in prep_chip_selects()
772 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;  in prep_chip_selects()
773 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;  in prep_chip_selects()
789 		u32 *base0 = &pvt->csels[0].csbases[cs];  in read_dct_base_mask()
790 		u32 *base1 = &pvt->csels[1].csbases[cs];  in read_dct_base_mask()
808 		u32 *mask0 = &pvt->csels[0].csmasks[cs];  in read_dct_base_mask()
809 		u32 *mask1 = &pvt->csels[1].csmasks[cs];  in read_dct_base_mask()
858 		dcsm = pvt->csels[0].csmasks[0];  in determine_memory_type()
1289 	u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr];  in f15_m60h_dbam_to_chip_select()
1850 	u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;  in debug_display_dimm_sizes()
1865 				 pvt->csels[1].csbases :  in debug_display_dimm_sizes()
1866 				 pvt->csels[0].csbases;  in debug_display_dimm_sizes()
1869 		dcsb = pvt->csels[1].csbases;  in debug_display_dimm_sizes()
2807 	layers[0].size = pvt->csels[0].b_cnt;  in init_one_instance()