118 	switch (pvt->fam) {  in amd64_read_dct_pci_cfg()
217 	if (pvt->fam == 0xf)  in set_scrub_rate()
221 	if (pvt->fam == 0x15 && pvt->model < 0x10)  in set_scrub_rate()
234 	if (pvt->fam == 0x15 && pvt->model < 0x10)  in get_scrub_rate()
349 	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {  in get_cs_base_and_mask()
360 	} else if (pvt->fam == 0x16 ||  in get_cs_base_and_mask()
361 		  (pvt->fam == 0x15 && pvt->model >= 0x30)) {  in get_cs_base_and_mask()
382 		if (pvt->fam == 0x15)  in get_cs_base_and_mask()
464 	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) {  in amd64_get_dram_hole_info()
471 	if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) {  in amd64_get_dram_hole_info()
503 	*hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt)  in amd64_get_dram_hole_info()
678 	bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)  in determine_edac_cap()
711 	if (pvt->fam == 0x10)  in debug_dump_dramcfg_low()
740 		 (pvt->fam == 0xf) ? k8_dhar_offset(pvt)  in dump_misc_regs()
748 	if (pvt->fam == 0xf)  in dump_misc_regs()
765 	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {  in prep_chip_selects()
768 	} else if (pvt->fam == 0x15 && pvt->model == 0x30) {  in prep_chip_selects()
796 		if (pvt->fam == 0xf)  in read_dct_base_mask()
801 				 cs, *base1, (pvt->fam == 0x10) ? reg1  in read_dct_base_mask()
815 		if (pvt->fam == 0xf)  in read_dct_base_mask()
820 				 cs, *mask1, (pvt->fam == 0x10) ? reg1  in read_dct_base_mask()
829 	switch (pvt->fam) {  in determine_memory_type()
875 		WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam);  in determine_memory_type()
917 	if (pvt->fam == 0xf) {  in get_error_address()
927 	if (pvt->fam == 0x15) {  in get_error_address()
995 	if (pvt->fam == 0xf)  in read_dram_base_limit_regs()
1005 	if (pvt->fam != 0x15)  in read_dram_base_limit_regs()
1166 	if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128))  in f1x_early_channel_count()
1333 	if (pvt->fam == 0xf)  in read_dram_ctl_register()
1540 			if (pvt->fam == 0x15 && pvt->model >= 0x30) {  in f1x_lookup_addr_in_dct()
1562 	if (pvt->fam == 0x10) {  in f1x_swap_interleaved_region()
1798 		if (pvt->fam == 0x15 && pvt->model >= 0x30)  in f1x_translate_sysaddr_to_cs()
1853 	if (pvt->fam == 0xf) {  in debug_display_dimm_sizes()
1861 	if (pvt->fam == 0x10) {  in debug_display_dimm_sizes()
2325 	if (pvt->fam >= 0x10) {  in read_mc_regs()
2328 		if (pvt->fam != 0x16)  in read_mc_regs()
2332 		if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25))  in read_mc_regs()
2426 		if (pvt->fam != 0xf)  in init_csrows()
2444 		if (pvt->fam != 0xf && row_dct1) {  in init_csrows()
2670 				 struct amd64_family_type *fam)  in setup_mci_misc_attrs()  argument
2686 	mci->ctl_name		= fam->ctl_name;  in setup_mci_misc_attrs()
2705 	pvt->fam	= boot_cpu_data.x86;  in per_family_init()
2707 	switch (pvt->fam) {  in per_family_init()
2749 		     (pvt->fam == 0xf ?  in per_family_init()