Lines Matching refs:reg
68 #define SAD_LIMIT(reg) ((GET_BITFIELD(reg, 6, 25) << 26) | 0x3ffffff) argument
69 #define DRAM_ATTR(reg) GET_BITFIELD(reg, 2, 3) argument
70 #define INTERLEAVE_MODE(reg) GET_BITFIELD(reg, 1, 1) argument
71 #define DRAM_RULE_ENABLE(reg) GET_BITFIELD(reg, 0, 0) argument
72 #define A7MODE(reg) GET_BITFIELD(reg, 26, 26) argument
74 static char *get_dram_attr(u32 reg) in get_dram_attr() argument
76 switch(DRAM_ATTR(reg)) { in get_dram_attr()
127 static inline int sad_pkg(const struct interleave_pkg *table, u32 reg, in sad_pkg() argument
130 return GET_BITFIELD(reg, table[interleave].start, in sad_pkg()
142 #define GET_TOLM(reg) ((GET_BITFIELD(reg, 0, 3) << 28) | 0x3ffffff) argument
143 #define GET_TOHM(reg) ((GET_BITFIELD(reg, 0, 20) << 25) | 0x3ffffff) argument
149 #define SOURCE_ID(reg) GET_BITFIELD(reg, 9, 11) argument
162 #define TAD_LIMIT(reg) ((GET_BITFIELD(reg, 12, 31) << 26) | 0x3ffffff) argument
163 #define TAD_SOCK(reg) GET_BITFIELD(reg, 10, 11) argument
164 #define TAD_CH(reg) GET_BITFIELD(reg, 8, 9) argument
165 #define TAD_TGT3(reg) GET_BITFIELD(reg, 6, 7) argument
166 #define TAD_TGT2(reg) GET_BITFIELD(reg, 4, 5) argument
167 #define TAD_TGT1(reg) GET_BITFIELD(reg, 2, 3) argument
168 #define TAD_TGT0(reg) GET_BITFIELD(reg, 0, 1) argument
181 #define IS_MIRROR_ENABLED(reg) GET_BITFIELD(reg, 0, 0) argument
200 #define CHN_IDX_OFFSET(reg) GET_BITFIELD(reg, 28, 29) argument
201 #define TAD_OFFSET(reg) (GET_BITFIELD(reg, 6, 25) << 26) argument
208 #define IS_RIR_VALID(reg) GET_BITFIELD(reg, 31, 31) argument
209 #define RIR_WAY(reg) GET_BITFIELD(reg, 28, 29) argument
221 #define RIR_RNK_TGT(type, reg) (((type) == BROADWELL) ? \ argument
222 GET_BITFIELD(reg, 20, 23) : GET_BITFIELD(reg, 16, 19))
224 #define RIR_OFFSET(type, reg) (((type) == HASWELL || (type) == BROADWELL) ? \ argument
225 GET_BITFIELD(reg, 2, 15) : GET_BITFIELD(reg, 2, 14))
237 #define RANK_ODD_OV(reg) GET_BITFIELD(reg, 31, 31) argument
238 #define RANK_ODD_ERR_CNT(reg) GET_BITFIELD(reg, 16, 30) argument
239 #define RANK_EVEN_OV(reg) GET_BITFIELD(reg, 15, 15) argument
240 #define RANK_EVEN_ERR_CNT(reg) GET_BITFIELD(reg, 0, 14) argument
246 #define RANK_ODD_ERR_THRSLD(reg) GET_BITFIELD(reg, 16, 30) argument
247 #define RANK_EVEN_ERR_THRSLD(reg) GET_BITFIELD(reg, 0, 14) argument
278 u64 (*rir_limit)(u32 reg);
647 u32 reg; in sbridge_get_tolm() local
650 pci_read_config_dword(pvt->pci_sad1, TOLM, ®); in sbridge_get_tolm()
651 return GET_TOLM(reg); in sbridge_get_tolm()
656 u32 reg; in sbridge_get_tohm() local
658 pci_read_config_dword(pvt->pci_sad1, TOHM, ®); in sbridge_get_tohm()
659 return GET_TOHM(reg); in sbridge_get_tohm()
664 u32 reg; in ibridge_get_tolm() local
666 pci_read_config_dword(pvt->pci_br1, TOLM, ®); in ibridge_get_tolm()
668 return GET_TOLM(reg); in ibridge_get_tolm()
673 u32 reg; in ibridge_get_tohm() local
675 pci_read_config_dword(pvt->pci_br1, TOHM, ®); in ibridge_get_tohm()
677 return GET_TOHM(reg); in ibridge_get_tohm()
680 static u64 rir_limit(u32 reg) in rir_limit() argument
682 return ((u64)GET_BITFIELD(reg, 1, 10) << 29) | 0x1fffffff; in rir_limit()
687 u32 reg; in get_memory_type() local
692 ®); in get_memory_type()
693 if (GET_BITFIELD(reg, 11, 11)) in get_memory_type()
706 u32 reg; in haswell_get_memory_type() local
714 HASWELL_DDRCRCLKCONTROLS, ®); in haswell_get_memory_type()
716 if (GET_BITFIELD(reg, 16, 16)) in haswell_get_memory_type()
719 pci_read_config_dword(pvt->pci_ta, MCMTR, ®); in haswell_get_memory_type()
720 if (GET_BITFIELD(reg, 14, 14)) { in haswell_get_memory_type()
738 u32 reg; in get_node_id() local
739 pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, ®); in get_node_id()
740 return GET_BITFIELD(reg, 0, 2); in get_node_id()
745 u32 reg; in haswell_get_node_id() local
747 pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, ®); in haswell_get_node_id()
748 return GET_BITFIELD(reg, 0, 3); in haswell_get_node_id()
753 u32 reg; in haswell_get_tolm() local
755 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, ®); in haswell_get_tolm()
756 return (GET_BITFIELD(reg, 26, 31) << 26) | 0x3ffffff; in haswell_get_tolm()
762 u32 reg; in haswell_get_tohm() local
764 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, ®); in haswell_get_tohm()
765 rc = GET_BITFIELD(reg, 26, 31); in haswell_get_tohm()
766 pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, ®); in haswell_get_tohm()
767 rc = ((reg << 6) | rc) << 26; in haswell_get_tohm()
772 static u64 haswell_rir_limit(u32 reg) in haswell_rir_limit() argument
774 return (((u64)GET_BITFIELD(reg, 1, 11) + 1) << 29) - 1; in haswell_rir_limit()
855 u32 reg; in get_dimm_config() local
860 pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, ®); in get_dimm_config()
862 pci_read_config_dword(pvt->pci_br0, SAD_TARGET, ®); in get_dimm_config()
864 pvt->sbridge_dev->source_id = SOURCE_ID(reg); in get_dimm_config()
872 pci_read_config_dword(pvt->pci_ras, RASENABLES, ®); in get_dimm_config()
873 if (IS_MIRROR_ENABLED(reg)) { in get_dimm_config()
965 u32 reg; in get_memory_layout() local
1000 ®); in get_memory_layout()
1001 limit = SAD_LIMIT(reg); in get_memory_layout()
1003 if (!DRAM_RULE_ENABLE(reg)) in get_memory_layout()
1013 get_dram_attr(reg), in get_memory_layout()
1016 INTERLEAVE_MODE(reg) ? "8:6" : "[8:6]XOR[18:16]", in get_memory_layout()
1017 reg); in get_memory_layout()
1021 ®); in get_memory_layout()
1022 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); in get_memory_layout()
1024 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j); in get_memory_layout()
1039 ®); in get_memory_layout()
1040 limit = TAD_LIMIT(reg); in get_memory_layout()
1049 (u32)(1 << TAD_SOCK(reg)), in get_memory_layout()
1050 (u32)TAD_CH(reg) + 1, in get_memory_layout()
1051 (u32)TAD_TGT0(reg), in get_memory_layout()
1052 (u32)TAD_TGT1(reg), in get_memory_layout()
1053 (u32)TAD_TGT2(reg), in get_memory_layout()
1054 (u32)TAD_TGT3(reg), in get_memory_layout()
1055 reg); in get_memory_layout()
1068 ®); in get_memory_layout()
1069 tmp_mb = TAD_OFFSET(reg) >> 20; in get_memory_layout()
1075 reg); in get_memory_layout()
1088 ®); in get_memory_layout()
1090 if (!IS_RIR_VALID(reg)) in get_memory_layout()
1093 tmp_mb = pvt->info.rir_limit(reg) >> 20; in get_memory_layout()
1094 rir_way = 1 << RIR_WAY(reg); in get_memory_layout()
1101 reg); in get_memory_layout()
1106 ®); in get_memory_layout()
1107 tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6; in get_memory_layout()
1114 (u32)RIR_RNK_TGT(pvt->info.type, reg), in get_memory_layout()
1115 reg); in get_memory_layout()
1146 u32 reg, dram_rule; in get_memory_error_data() local
1175 ®); in get_memory_error_data()
1177 if (!DRAM_RULE_ENABLE(reg)) in get_memory_error_data()
1180 limit = SAD_LIMIT(reg); in get_memory_error_data()
1193 dram_rule = reg; in get_memory_error_data()
1198 ®); in get_memory_error_data()
1201 sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0); in get_memory_error_data()
1203 u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way); in get_memory_error_data()
1257 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); in get_memory_error_data()
1264 HASWELL_HASYSDEFEATURE2, ®); in get_memory_error_data()
1265 shiftup = GET_BITFIELD(reg, 22, 22); in get_memory_error_data()
1273 pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx); in get_memory_error_data()
1306 pci_read_config_dword(pci_ha, tad_dram_rule[n_tads], ®); in get_memory_error_data()
1307 limit = TAD_LIMIT(reg); in get_memory_error_data()
1321 ch_way = TAD_CH(reg) + 1; in get_memory_error_data()
1322 sck_way = TAD_SOCK(reg); in get_memory_error_data()
1335 base_ch = TAD_TGT0(reg); in get_memory_error_data()
1338 base_ch = TAD_TGT1(reg); in get_memory_error_data()
1341 base_ch = TAD_TGT2(reg); in get_memory_error_data()
1344 base_ch = TAD_TGT3(reg); in get_memory_error_data()
1407 ®); in get_memory_error_data()
1409 if (!IS_RIR_VALID(reg)) in get_memory_error_data()
1412 limit = pvt->info.rir_limit(reg); in get_memory_error_data()
1418 1 << RIR_WAY(reg)); in get_memory_error_data()
1427 rir_way = RIR_WAY(reg); in get_memory_error_data()
1437 ®); in get_memory_error_data()
1438 *rank = RIR_RNK_TGT(pvt->info.type, reg); in get_memory_error_data()