116 static void crystalcove_update_irq_mask(struct crystalcove_gpio *cg,  in crystalcove_update_irq_mask()  argument
122 	if (cg->set_irq_mask)  in crystalcove_update_irq_mask()
123 		regmap_update_bits(cg->regmap, mirqs0, mask, mask);  in crystalcove_update_irq_mask()
125 		regmap_update_bits(cg->regmap, mirqs0, mask, 0);  in crystalcove_update_irq_mask()
128 static void crystalcove_update_irq_ctrl(struct crystalcove_gpio *cg, int gpio)  in crystalcove_update_irq_ctrl()  argument
132 	regmap_update_bits(cg->regmap, reg, CTLI_INTCNT_BE, cg->intcnt_value);  in crystalcove_update_irq_ctrl()
137 	struct crystalcove_gpio *cg = to_cg(chip);  in crystalcove_gpio_dir_in()  local
142 	return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),  in crystalcove_gpio_dir_in()
149 	struct crystalcove_gpio *cg = to_cg(chip);  in crystalcove_gpio_dir_out()  local
154 	return regmap_write(cg->regmap, to_reg(gpio, CTRL_OUT),  in crystalcove_gpio_dir_out()
160 	struct crystalcove_gpio *cg = to_cg(chip);  in crystalcove_gpio_get()  local
167 	ret = regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &val);  in crystalcove_gpio_get()
177 	struct crystalcove_gpio *cg = to_cg(chip);  in crystalcove_gpio_set()  local
183 		regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 1);  in crystalcove_gpio_set()
185 		regmap_update_bits(cg->regmap, to_reg(gpio, CTRL_OUT), 1, 0);  in crystalcove_gpio_set()
190 	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));  in crystalcove_irq_type()  local
194 		cg->intcnt_value = CTLI_INTCNT_DIS;  in crystalcove_irq_type()
197 		cg->intcnt_value = CTLI_INTCNT_BE;  in crystalcove_irq_type()
200 		cg->intcnt_value = CTLI_INTCNT_PE;  in crystalcove_irq_type()
203 		cg->intcnt_value = CTLI_INTCNT_NE;  in crystalcove_irq_type()
209 	cg->update |= UPDATE_IRQ_TYPE;  in crystalcove_irq_type()
216 	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));  in crystalcove_bus_lock()  local
218 	mutex_lock(&cg->buslock);  in crystalcove_bus_lock()
223 	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));  in crystalcove_bus_sync_unlock()  local
226 	if (cg->update & UPDATE_IRQ_TYPE)  in crystalcove_bus_sync_unlock()
227 		crystalcove_update_irq_ctrl(cg, gpio);  in crystalcove_bus_sync_unlock()
228 	if (cg->update & UPDATE_IRQ_MASK)  in crystalcove_bus_sync_unlock()
229 		crystalcove_update_irq_mask(cg, gpio);  in crystalcove_bus_sync_unlock()
230 	cg->update = 0;  in crystalcove_bus_sync_unlock()
232 	mutex_unlock(&cg->buslock);  in crystalcove_bus_sync_unlock()
237 	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));  in crystalcove_irq_unmask()  local
239 	cg->set_irq_mask = false;  in crystalcove_irq_unmask()
240 	cg->update |= UPDATE_IRQ_MASK;  in crystalcove_irq_unmask()
245 	struct crystalcove_gpio *cg = to_cg(irq_data_get_irq_chip_data(data));  in crystalcove_irq_mask()  local
247 	cg->set_irq_mask = true;  in crystalcove_irq_mask()
248 	cg->update |= UPDATE_IRQ_MASK;  in crystalcove_irq_mask()
263 	struct crystalcove_gpio *cg = data;  in crystalcove_gpio_irq_handler()  local
269 	if (regmap_read(cg->regmap, GPIO0IRQ, &p0) ||  in crystalcove_gpio_irq_handler()
270 	    regmap_read(cg->regmap, GPIO1IRQ, &p1))  in crystalcove_gpio_irq_handler()
273 	regmap_write(cg->regmap, GPIO0IRQ, p0);  in crystalcove_gpio_irq_handler()
274 	regmap_write(cg->regmap, GPIO1IRQ, p1);  in crystalcove_gpio_irq_handler()
280 			virq = irq_find_mapping(cg->chip.irqdomain, gpio);  in crystalcove_gpio_irq_handler()
291 	struct crystalcove_gpio *cg = to_cg(chip);  in crystalcove_gpio_dbg_show()  local
296 		regmap_read(cg->regmap, to_reg(gpio, CTRL_OUT), &ctlo);  in crystalcove_gpio_dbg_show()
297 		regmap_read(cg->regmap, to_reg(gpio, CTRL_IN), &ctli);  in crystalcove_gpio_dbg_show()
298 		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQS0 : MGPIO1IRQS0,  in crystalcove_gpio_dbg_show()
300 		regmap_read(cg->regmap, gpio < 8 ? MGPIO0IRQSX : MGPIO1IRQSX,  in crystalcove_gpio_dbg_show()
302 		regmap_read(cg->regmap, gpio < 8 ? GPIO0IRQ : GPIO1IRQ,  in crystalcove_gpio_dbg_show()
321 	struct crystalcove_gpio *cg;  in crystalcove_gpio_probe()  local
329 	cg = devm_kzalloc(&pdev->dev, sizeof(*cg), GFP_KERNEL);  in crystalcove_gpio_probe()
330 	if (!cg)  in crystalcove_gpio_probe()
333 	platform_set_drvdata(pdev, cg);  in crystalcove_gpio_probe()
335 	mutex_init(&cg->buslock);  in crystalcove_gpio_probe()
336 	cg->chip.label = KBUILD_MODNAME;  in crystalcove_gpio_probe()
337 	cg->chip.direction_input = crystalcove_gpio_dir_in;  in crystalcove_gpio_probe()
338 	cg->chip.direction_output = crystalcove_gpio_dir_out;  in crystalcove_gpio_probe()
339 	cg->chip.get = crystalcove_gpio_get;  in crystalcove_gpio_probe()
340 	cg->chip.set = crystalcove_gpio_set;  in crystalcove_gpio_probe()
341 	cg->chip.base = -1;  in crystalcove_gpio_probe()
342 	cg->chip.ngpio = CRYSTALCOVE_VGPIO_NUM;  in crystalcove_gpio_probe()
343 	cg->chip.can_sleep = true;  in crystalcove_gpio_probe()
344 	cg->chip.dev = dev;  in crystalcove_gpio_probe()
345 	cg->chip.dbg_show = crystalcove_gpio_dbg_show;  in crystalcove_gpio_probe()
346 	cg->regmap = pmic->regmap;  in crystalcove_gpio_probe()
348 	retval = gpiochip_add(&cg->chip);  in crystalcove_gpio_probe()
354 	gpiochip_irqchip_add(&cg->chip, &crystalcove_irqchip, 0,  in crystalcove_gpio_probe()
358 				      IRQF_ONESHOT, KBUILD_MODNAME, cg);  in crystalcove_gpio_probe()
368 	gpiochip_remove(&cg->chip);  in crystalcove_gpio_probe()
374 	struct crystalcove_gpio *cg = platform_get_drvdata(pdev);  in crystalcove_gpio_remove()  local
377 	gpiochip_remove(&cg->chip);  in crystalcove_gpio_remove()
379 		free_irq(irq, cg);  in crystalcove_gpio_remove()