119 	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);  in ioh_gpio_set()
142 	iowrite32(pm, &chip->reg->regs[chip->ch].pm);  in ioh_gpio_direction_output()
149 	iowrite32(reg_val, &chip->reg->regs[chip->ch].po);  in ioh_gpio_direction_output()
166 	iowrite32(pm, &chip->reg->regs[chip->ch].pm);  in ioh_gpio_direction_input()
207 		iowrite32(chip->ioh_gpio_reg.po_reg,  in ioh_gpio_restore_reg_conf()
209 		iowrite32(chip->ioh_gpio_reg.pm_reg,  in ioh_gpio_restore_reg_conf()
211 		iowrite32(chip->ioh_gpio_reg.ien_reg,  in ioh_gpio_restore_reg_conf()
213 		iowrite32(chip->ioh_gpio_reg.imask_reg,  in ioh_gpio_restore_reg_conf()
215 		iowrite32(chip->ioh_gpio_reg.im0_reg,  in ioh_gpio_restore_reg_conf()
217 		iowrite32(chip->ioh_gpio_reg.im1_reg,  in ioh_gpio_restore_reg_conf()
220 			iowrite32(chip->ioh_gpio_reg.use_sel_reg,  in ioh_gpio_restore_reg_conf()
301 	iowrite32(im | (val << (im_pos * 4)), im_reg);  in ioh_irq_type()
304 	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].iclr);  in ioh_irq_type()
307 	iowrite32(BIT(ch), &chip->reg->regs[chip->ch].imaskclr);  in ioh_irq_type()
311 	iowrite32(ien | BIT(ch), &chip->reg->regs[chip->ch].ien);  in ioh_irq_type()
323 	iowrite32(1 << (d->irq - chip->irq_base),  in ioh_irq_unmask()
332 	iowrite32(1 << (d->irq - chip->irq_base),  in ioh_irq_mask()
346 	iowrite32(ien, &chip->reg->regs[chip->ch].ien);  in ioh_irq_disable()
360 	iowrite32(ien, &chip->reg->regs[chip->ch].ien);  in ioh_irq_enable()
378 				iowrite32(BIT(j),  in ioh_gpio_handler()
583 	iowrite32(0x01, &chip->reg->srst);  in ioh_gpio_resume()
584 	iowrite32(0x00, &chip->reg->srst);  in ioh_gpio_resume()