78 	void (*set_dataout)(struct gpio_bank *bank, unsigned gpio, int enable);
86 #define BANK_USED(bank) (bank->mod_usage || bank->irq_usage)  argument
97 static void omap_set_gpio_direction(struct gpio_bank *bank, int gpio,  in omap_set_gpio_direction()  argument
100 	void __iomem *reg = bank->base;  in omap_set_gpio_direction()
103 	reg += bank->regs->direction;  in omap_set_gpio_direction()
110 	bank->context.oe = l;  in omap_set_gpio_direction()
115 static void omap_set_gpio_dataout_reg(struct gpio_bank *bank, unsigned offset,  in omap_set_gpio_dataout_reg()  argument
118 	void __iomem *reg = bank->base;  in omap_set_gpio_dataout_reg()
122 		reg += bank->regs->set_dataout;  in omap_set_gpio_dataout_reg()
123 		bank->context.dataout |= l;  in omap_set_gpio_dataout_reg()
125 		reg += bank->regs->clr_dataout;  in omap_set_gpio_dataout_reg()
126 		bank->context.dataout &= ~l;  in omap_set_gpio_dataout_reg()
133 static void omap_set_gpio_dataout_mask(struct gpio_bank *bank, unsigned offset,  in omap_set_gpio_dataout_mask()  argument
136 	void __iomem *reg = bank->base + bank->regs->dataout;  in omap_set_gpio_dataout_mask()
146 	bank->context.dataout = l;  in omap_set_gpio_dataout_mask()
149 static int omap_get_gpio_datain(struct gpio_bank *bank, int offset)  in omap_get_gpio_datain()  argument
151 	void __iomem *reg = bank->base + bank->regs->datain;  in omap_get_gpio_datain()
156 static int omap_get_gpio_dataout(struct gpio_bank *bank, int offset)  in omap_get_gpio_dataout()  argument
158 	void __iomem *reg = bank->base + bank->regs->dataout;  in omap_get_gpio_dataout()
175 static inline void omap_gpio_dbck_enable(struct gpio_bank *bank)  in omap_gpio_dbck_enable()  argument
177 	if (bank->dbck_enable_mask && !bank->dbck_enabled) {  in omap_gpio_dbck_enable()
178 		clk_prepare_enable(bank->dbck);  in omap_gpio_dbck_enable()
179 		bank->dbck_enabled = true;  in omap_gpio_dbck_enable()
181 		writel_relaxed(bank->dbck_enable_mask,  in omap_gpio_dbck_enable()
182 			     bank->base + bank->regs->debounce_en);  in omap_gpio_dbck_enable()
186 static inline void omap_gpio_dbck_disable(struct gpio_bank *bank)  in omap_gpio_dbck_disable()  argument
188 	if (bank->dbck_enable_mask && bank->dbck_enabled) {  in omap_gpio_dbck_disable()
194 		writel_relaxed(0, bank->base + bank->regs->debounce_en);  in omap_gpio_dbck_disable()
196 		clk_disable_unprepare(bank->dbck);  in omap_gpio_dbck_disable()
197 		bank->dbck_enabled = false;  in omap_gpio_dbck_disable()
210 static void omap2_set_gpio_debounce(struct gpio_bank *bank, unsigned offset,  in omap2_set_gpio_debounce()  argument
217 	if (!bank->dbck_flag)  in omap2_set_gpio_debounce()
229 	clk_prepare_enable(bank->dbck);  in omap2_set_gpio_debounce()
230 	reg = bank->base + bank->regs->debounce;  in omap2_set_gpio_debounce()
233 	reg = bank->base + bank->regs->debounce_en;  in omap2_set_gpio_debounce()
240 	bank->dbck_enable_mask = val;  in omap2_set_gpio_debounce()
243 	clk_disable_unprepare(bank->dbck);  in omap2_set_gpio_debounce()
252 	omap_gpio_dbck_enable(bank);  in omap2_set_gpio_debounce()
253 	if (bank->dbck_enable_mask) {  in omap2_set_gpio_debounce()
254 		bank->context.debounce = debounce;  in omap2_set_gpio_debounce()
255 		bank->context.debounce_en = val;  in omap2_set_gpio_debounce()
269 static void omap_clear_gpio_debounce(struct gpio_bank *bank, unsigned offset)  in omap_clear_gpio_debounce()  argument
273 	if (!bank->dbck_flag)  in omap_clear_gpio_debounce()
276 	if (!(bank->dbck_enable_mask & gpio_bit))  in omap_clear_gpio_debounce()
279 	bank->dbck_enable_mask &= ~gpio_bit;  in omap_clear_gpio_debounce()
280 	bank->context.debounce_en &= ~gpio_bit;  in omap_clear_gpio_debounce()
281         writel_relaxed(bank->context.debounce_en,  in omap_clear_gpio_debounce()
282 		     bank->base + bank->regs->debounce_en);  in omap_clear_gpio_debounce()
284 	if (!bank->dbck_enable_mask) {  in omap_clear_gpio_debounce()
285 		bank->context.debounce = 0;  in omap_clear_gpio_debounce()
286 		writel_relaxed(bank->context.debounce, bank->base +  in omap_clear_gpio_debounce()
287 			     bank->regs->debounce);  in omap_clear_gpio_debounce()
288 		clk_disable_unprepare(bank->dbck);  in omap_clear_gpio_debounce()
289 		bank->dbck_enabled = false;  in omap_clear_gpio_debounce()
293 static inline void omap_set_gpio_trigger(struct gpio_bank *bank, int gpio,  in omap_set_gpio_trigger()  argument
296 	void __iomem *base = bank->base;  in omap_set_gpio_trigger()
299 	omap_gpio_rmw(base, bank->regs->leveldetect0, gpio_bit,  in omap_set_gpio_trigger()
301 	omap_gpio_rmw(base, bank->regs->leveldetect1, gpio_bit,  in omap_set_gpio_trigger()
303 	omap_gpio_rmw(base, bank->regs->risingdetect, gpio_bit,  in omap_set_gpio_trigger()
305 	omap_gpio_rmw(base, bank->regs->fallingdetect, gpio_bit,  in omap_set_gpio_trigger()
308 	bank->context.leveldetect0 =  in omap_set_gpio_trigger()
309 			readl_relaxed(bank->base + bank->regs->leveldetect0);  in omap_set_gpio_trigger()
310 	bank->context.leveldetect1 =  in omap_set_gpio_trigger()
311 			readl_relaxed(bank->base + bank->regs->leveldetect1);  in omap_set_gpio_trigger()
312 	bank->context.risingdetect =  in omap_set_gpio_trigger()
313 			readl_relaxed(bank->base + bank->regs->risingdetect);  in omap_set_gpio_trigger()
314 	bank->context.fallingdetect =  in omap_set_gpio_trigger()
315 			readl_relaxed(bank->base + bank->regs->fallingdetect);  in omap_set_gpio_trigger()
317 	if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {  in omap_set_gpio_trigger()
318 		omap_gpio_rmw(base, bank->regs->wkup_en, gpio_bit, trigger != 0);  in omap_set_gpio_trigger()
319 		bank->context.wake_en =  in omap_set_gpio_trigger()
320 			readl_relaxed(bank->base + bank->regs->wkup_en);  in omap_set_gpio_trigger()
324 	if (!bank->regs->irqctrl) {  in omap_set_gpio_trigger()
326 		if (bank->non_wakeup_gpios) {  in omap_set_gpio_trigger()
327 			if (!(bank->non_wakeup_gpios & gpio_bit))  in omap_set_gpio_trigger()
338 			bank->enabled_non_wakeup_gpios |= gpio_bit;  in omap_set_gpio_trigger()
340 			bank->enabled_non_wakeup_gpios &= ~gpio_bit;  in omap_set_gpio_trigger()
344 	bank->level_mask =  in omap_set_gpio_trigger()
345 		readl_relaxed(bank->base + bank->regs->leveldetect0) |  in omap_set_gpio_trigger()
346 		readl_relaxed(bank->base + bank->regs->leveldetect1);  in omap_set_gpio_trigger()
354 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)  in omap_toggle_gpio_edge_triggering()  argument
356 	void __iomem *reg = bank->base;  in omap_toggle_gpio_edge_triggering()
359 	if (!bank->regs->irqctrl)  in omap_toggle_gpio_edge_triggering()
362 	reg += bank->regs->irqctrl;  in omap_toggle_gpio_edge_triggering()
373 static void omap_toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio) {}  in omap_toggle_gpio_edge_triggering()  argument
376 static int omap_set_gpio_triggering(struct gpio_bank *bank, int gpio,  in omap_set_gpio_triggering()  argument
379 	void __iomem *reg = bank->base;  in omap_set_gpio_triggering()
380 	void __iomem *base = bank->base;  in omap_set_gpio_triggering()
383 	if (bank->regs->leveldetect0 && bank->regs->wkup_en) {  in omap_set_gpio_triggering()
384 		omap_set_gpio_trigger(bank, gpio, trigger);  in omap_set_gpio_triggering()
385 	} else if (bank->regs->irqctrl) {  in omap_set_gpio_triggering()
386 		reg += bank->regs->irqctrl;  in omap_set_gpio_triggering()
390 			bank->toggle_mask |= BIT(gpio);  in omap_set_gpio_triggering()
399 	} else if (bank->regs->edgectrl1) {  in omap_set_gpio_triggering()
401 			reg += bank->regs->edgectrl2;  in omap_set_gpio_triggering()
403 			reg += bank->regs->edgectrl1;  in omap_set_gpio_triggering()
414 		omap_gpio_rmw(base, bank->regs->wkup_en, BIT(gpio), trigger);  in omap_set_gpio_triggering()
415 		bank->context.wake_en =  in omap_set_gpio_triggering()
416 			readl_relaxed(bank->base + bank->regs->wkup_en);  in omap_set_gpio_triggering()
422 static void omap_enable_gpio_module(struct gpio_bank *bank, unsigned offset)  in omap_enable_gpio_module()  argument
424 	if (bank->regs->pinctrl) {  in omap_enable_gpio_module()
425 		void __iomem *reg = bank->base + bank->regs->pinctrl;  in omap_enable_gpio_module()
431 	if (bank->regs->ctrl && !BANK_USED(bank)) {  in omap_enable_gpio_module()
432 		void __iomem *reg = bank->base + bank->regs->ctrl;  in omap_enable_gpio_module()
439 		bank->context.ctrl = ctrl;  in omap_enable_gpio_module()
443 static void omap_disable_gpio_module(struct gpio_bank *bank, unsigned offset)  in omap_disable_gpio_module()  argument
445 	void __iomem *base = bank->base;  in omap_disable_gpio_module()
447 	if (bank->regs->wkup_en &&  in omap_disable_gpio_module()
448 	    !LINE_USED(bank->mod_usage, offset) &&  in omap_disable_gpio_module()
449 	    !LINE_USED(bank->irq_usage, offset)) {  in omap_disable_gpio_module()
451 		omap_gpio_rmw(base, bank->regs->wkup_en, BIT(offset), 0);  in omap_disable_gpio_module()
452 		bank->context.wake_en =  in omap_disable_gpio_module()
453 			readl_relaxed(bank->base + bank->regs->wkup_en);  in omap_disable_gpio_module()
456 	if (bank->regs->ctrl && !BANK_USED(bank)) {  in omap_disable_gpio_module()
457 		void __iomem *reg = bank->base + bank->regs->ctrl;  in omap_disable_gpio_module()
464 		bank->context.ctrl = ctrl;  in omap_disable_gpio_module()
468 static int omap_gpio_is_input(struct gpio_bank *bank, unsigned offset)  in omap_gpio_is_input()  argument
470 	void __iomem *reg = bank->base + bank->regs->direction;  in omap_gpio_is_input()
475 static void omap_gpio_init_irq(struct gpio_bank *bank, unsigned offset)  in omap_gpio_init_irq()  argument
477 	if (!LINE_USED(bank->mod_usage, offset)) {  in omap_gpio_init_irq()
478 		omap_enable_gpio_module(bank, offset);  in omap_gpio_init_irq()
479 		omap_set_gpio_direction(bank, offset, 1);  in omap_gpio_init_irq()
481 	bank->irq_usage |= BIT(offset);  in omap_gpio_init_irq()
486 	struct gpio_bank *bank = omap_irq_data_get_bank(d);  in omap_gpio_irq_type()  local
491 	if (!BANK_USED(bank))  in omap_gpio_irq_type()
492 		pm_runtime_get_sync(bank->dev);  in omap_gpio_irq_type()
497 	if (!bank->regs->leveldetect0 &&  in omap_gpio_irq_type()
501 	spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_irq_type()
502 	retval = omap_set_gpio_triggering(bank, offset, type);  in omap_gpio_irq_type()
503 	omap_gpio_init_irq(bank, offset);  in omap_gpio_irq_type()
504 	if (!omap_gpio_is_input(bank, offset)) {  in omap_gpio_irq_type()
505 		spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_irq_type()
508 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_irq_type()
518 static void omap_clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)  in omap_clear_gpio_irqbank()  argument
520 	void __iomem *reg = bank->base;  in omap_clear_gpio_irqbank()
522 	reg += bank->regs->irqstatus;  in omap_clear_gpio_irqbank()
526 	if (bank->regs->irqstatus2) {  in omap_clear_gpio_irqbank()
527 		reg = bank->base + bank->regs->irqstatus2;  in omap_clear_gpio_irqbank()
535 static inline void omap_clear_gpio_irqstatus(struct gpio_bank *bank,  in omap_clear_gpio_irqstatus()  argument
538 	omap_clear_gpio_irqbank(bank, BIT(offset));  in omap_clear_gpio_irqstatus()
541 static u32 omap_get_gpio_irqbank_mask(struct gpio_bank *bank)  in omap_get_gpio_irqbank_mask()  argument
543 	void __iomem *reg = bank->base;  in omap_get_gpio_irqbank_mask()
545 	u32 mask = (BIT(bank->width)) - 1;  in omap_get_gpio_irqbank_mask()
547 	reg += bank->regs->irqenable;  in omap_get_gpio_irqbank_mask()
549 	if (bank->regs->irqenable_inv)  in omap_get_gpio_irqbank_mask()
555 static void omap_enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)  in omap_enable_gpio_irqbank()  argument
557 	void __iomem *reg = bank->base;  in omap_enable_gpio_irqbank()
560 	if (bank->regs->set_irqenable) {  in omap_enable_gpio_irqbank()
561 		reg += bank->regs->set_irqenable;  in omap_enable_gpio_irqbank()
563 		bank->context.irqenable1 |= gpio_mask;  in omap_enable_gpio_irqbank()
565 		reg += bank->regs->irqenable;  in omap_enable_gpio_irqbank()
567 		if (bank->regs->irqenable_inv)  in omap_enable_gpio_irqbank()
571 		bank->context.irqenable1 = l;  in omap_enable_gpio_irqbank()
577 static void omap_disable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)  in omap_disable_gpio_irqbank()  argument
579 	void __iomem *reg = bank->base;  in omap_disable_gpio_irqbank()
582 	if (bank->regs->clr_irqenable) {  in omap_disable_gpio_irqbank()
583 		reg += bank->regs->clr_irqenable;  in omap_disable_gpio_irqbank()
585 		bank->context.irqenable1 &= ~gpio_mask;  in omap_disable_gpio_irqbank()
587 		reg += bank->regs->irqenable;  in omap_disable_gpio_irqbank()
589 		if (bank->regs->irqenable_inv)  in omap_disable_gpio_irqbank()
593 		bank->context.irqenable1 = l;  in omap_disable_gpio_irqbank()
599 static inline void omap_set_gpio_irqenable(struct gpio_bank *bank,  in omap_set_gpio_irqenable()  argument
603 		omap_enable_gpio_irqbank(bank, BIT(offset));  in omap_set_gpio_irqenable()
605 		omap_disable_gpio_irqbank(bank, BIT(offset));  in omap_set_gpio_irqenable()
616 static int omap_set_gpio_wakeup(struct gpio_bank *bank, unsigned offset,  in omap_set_gpio_wakeup()  argument
622 	if (bank->non_wakeup_gpios & gpio_bit) {  in omap_set_gpio_wakeup()
623 		dev_err(bank->dev,  in omap_set_gpio_wakeup()
629 	spin_lock_irqsave(&bank->lock, flags);  in omap_set_gpio_wakeup()
631 		bank->context.wake_en |= gpio_bit;  in omap_set_gpio_wakeup()
633 		bank->context.wake_en &= ~gpio_bit;  in omap_set_gpio_wakeup()
635 	writel_relaxed(bank->context.wake_en, bank->base + bank->regs->wkup_en);  in omap_set_gpio_wakeup()
636 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_set_gpio_wakeup()
641 static void omap_reset_gpio(struct gpio_bank *bank, unsigned offset)  in omap_reset_gpio()  argument
643 	omap_set_gpio_direction(bank, offset, 1);  in omap_reset_gpio()
644 	omap_set_gpio_irqenable(bank, offset, 0);  in omap_reset_gpio()
645 	omap_clear_gpio_irqstatus(bank, offset);  in omap_reset_gpio()
646 	omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);  in omap_reset_gpio()
647 	omap_clear_gpio_debounce(bank, offset);  in omap_reset_gpio()
653 	struct gpio_bank *bank = omap_irq_data_get_bank(d);  in omap_gpio_wake_enable()  local
656 	return omap_set_gpio_wakeup(bank, offset, enable);  in omap_gpio_wake_enable()
661 	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_request()  local
668 	if (!BANK_USED(bank))  in omap_gpio_request()
669 		pm_runtime_get_sync(bank->dev);  in omap_gpio_request()
671 	spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_request()
676 	if (!LINE_USED(bank->irq_usage, offset)) {  in omap_gpio_request()
677 		omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);  in omap_gpio_request()
678 		omap_enable_gpio_module(bank, offset);  in omap_gpio_request()
680 	bank->mod_usage |= BIT(offset);  in omap_gpio_request()
681 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_request()
688 	struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_free()  local
691 	spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_free()
692 	bank->mod_usage &= ~(BIT(offset));  in omap_gpio_free()
693 	omap_disable_gpio_module(bank, offset);  in omap_gpio_free()
694 	omap_reset_gpio(bank, offset);  in omap_gpio_free()
695 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_free()
701 	if (!BANK_USED(bank))  in omap_gpio_free()
702 		pm_runtime_put(bank->dev);  in omap_gpio_free()
719 	struct gpio_bank *bank;  in omap_gpio_irq_handler()  local
726 	bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_irq_handler()
727 	isr_reg = bank->base + bank->regs->irqstatus;  in omap_gpio_irq_handler()
728 	pm_runtime_get_sync(bank->dev);  in omap_gpio_irq_handler()
737 		enabled = omap_get_gpio_irqbank_mask(bank);  in omap_gpio_irq_handler()
740 		if (bank->level_mask)  in omap_gpio_irq_handler()
741 			level_mask = bank->level_mask & enabled;  in omap_gpio_irq_handler()
746 		omap_disable_gpio_irqbank(bank, isr_saved & ~level_mask);  in omap_gpio_irq_handler()
747 		omap_clear_gpio_irqbank(bank, isr_saved & ~level_mask);  in omap_gpio_irq_handler()
748 		omap_enable_gpio_irqbank(bank, isr_saved & ~level_mask);  in omap_gpio_irq_handler()
771 			if (bank->toggle_mask & (BIT(bit)))  in omap_gpio_irq_handler()
772 				omap_toggle_gpio_edge_triggering(bank, bit);  in omap_gpio_irq_handler()
774 			generic_handle_irq(irq_find_mapping(bank->chip.irqdomain,  in omap_gpio_irq_handler()
785 	pm_runtime_put(bank->dev);  in omap_gpio_irq_handler()
790 	struct gpio_bank *bank = omap_irq_data_get_bank(d);  in omap_gpio_irq_startup()  local
794 	if (!BANK_USED(bank))  in omap_gpio_irq_startup()
795 		pm_runtime_get_sync(bank->dev);  in omap_gpio_irq_startup()
797 	spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_irq_startup()
798 	omap_gpio_init_irq(bank, offset);  in omap_gpio_irq_startup()
799 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_irq_startup()
807 	struct gpio_bank *bank = omap_irq_data_get_bank(d);  in omap_gpio_irq_shutdown()  local
811 	spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_irq_shutdown()
812 	bank->irq_usage &= ~(BIT(offset));  in omap_gpio_irq_shutdown()
813 	omap_disable_gpio_module(bank, offset);  in omap_gpio_irq_shutdown()
814 	omap_reset_gpio(bank, offset);  in omap_gpio_irq_shutdown()
815 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_irq_shutdown()
821 	if (!BANK_USED(bank))  in omap_gpio_irq_shutdown()
822 		pm_runtime_put(bank->dev);  in omap_gpio_irq_shutdown()
827 	struct gpio_bank *bank = omap_irq_data_get_bank(d);  in omap_gpio_ack_irq()  local
830 	omap_clear_gpio_irqstatus(bank, offset);  in omap_gpio_ack_irq()
835 	struct gpio_bank *bank = omap_irq_data_get_bank(d);  in omap_gpio_mask_irq()  local
839 	spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_mask_irq()
840 	omap_set_gpio_irqenable(bank, offset, 0);  in omap_gpio_mask_irq()
841 	omap_set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);  in omap_gpio_mask_irq()
842 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_mask_irq()
847 	struct gpio_bank *bank = omap_irq_data_get_bank(d);  in omap_gpio_unmask_irq()  local
852 	spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_unmask_irq()
854 		omap_set_gpio_triggering(bank, offset, trigger);  in omap_gpio_unmask_irq()
858 	if (bank->level_mask & BIT(offset)) {  in omap_gpio_unmask_irq()
859 		omap_set_gpio_irqenable(bank, offset, 0);  in omap_gpio_unmask_irq()
860 		omap_clear_gpio_irqstatus(bank, offset);  in omap_gpio_unmask_irq()
863 	omap_set_gpio_irqenable(bank, offset, 1);  in omap_gpio_unmask_irq()
864 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_unmask_irq()
872 	struct gpio_bank	*bank = platform_get_drvdata(pdev);  in omap_mpuio_suspend_noirq()  local
873 	void __iomem		*mask_reg = bank->base +  in omap_mpuio_suspend_noirq()
874 					OMAP_MPUIO_GPIO_MASKIT / bank->stride;  in omap_mpuio_suspend_noirq()
877 	spin_lock_irqsave(&bank->lock, flags);  in omap_mpuio_suspend_noirq()
878 	writel_relaxed(0xffff & ~bank->context.wake_en, mask_reg);  in omap_mpuio_suspend_noirq()
879 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_mpuio_suspend_noirq()
887 	struct gpio_bank	*bank = platform_get_drvdata(pdev);  in omap_mpuio_resume_noirq()  local
888 	void __iomem		*mask_reg = bank->base +  in omap_mpuio_resume_noirq()
889 					OMAP_MPUIO_GPIO_MASKIT / bank->stride;  in omap_mpuio_resume_noirq()
892 	spin_lock_irqsave(&bank->lock, flags);  in omap_mpuio_resume_noirq()
893 	writel_relaxed(bank->context.wake_en, mask_reg);  in omap_mpuio_resume_noirq()
894 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_mpuio_resume_noirq()
921 static inline void omap_mpuio_init(struct gpio_bank *bank)  in omap_mpuio_init()  argument
923 	platform_set_drvdata(&omap_mpuio_device, bank);  in omap_mpuio_init()
933 	struct gpio_bank *bank;  in omap_gpio_get_direction()  local
938 	bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_get_direction()
939 	reg = bank->base + bank->regs->direction;  in omap_gpio_get_direction()
940 	spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_get_direction()
942 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_get_direction()
948 	struct gpio_bank *bank;  in omap_gpio_input()  local
951 	bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_input()
952 	spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_input()
953 	omap_set_gpio_direction(bank, offset, 1);  in omap_gpio_input()
954 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_input()
960 	struct gpio_bank *bank;  in omap_gpio_get()  local
962 	bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_get()
964 	if (omap_gpio_is_input(bank, offset))  in omap_gpio_get()
965 		return omap_get_gpio_datain(bank, offset);  in omap_gpio_get()
967 		return omap_get_gpio_dataout(bank, offset);  in omap_gpio_get()
972 	struct gpio_bank *bank;  in omap_gpio_output()  local
975 	bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_output()
976 	spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_output()
977 	bank->set_dataout(bank, offset, value);  in omap_gpio_output()
978 	omap_set_gpio_direction(bank, offset, 0);  in omap_gpio_output()
979 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_output()
986 	struct gpio_bank *bank;  in omap_gpio_debounce()  local
989 	bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_debounce()
991 	spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_debounce()
992 	omap2_set_gpio_debounce(bank, offset, debounce);  in omap_gpio_debounce()
993 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_debounce()
1000 	struct gpio_bank *bank;  in omap_gpio_set()  local
1003 	bank = container_of(chip, struct gpio_bank, chip);  in omap_gpio_set()
1004 	spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_set()
1005 	bank->set_dataout(bank, offset, value);  in omap_gpio_set()
1006 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_set()
1011 static void __init omap_gpio_show_rev(struct gpio_bank *bank)  in omap_gpio_show_rev()  argument
1016 	if (called || bank->regs->revision == USHRT_MAX)  in omap_gpio_show_rev()
1019 	rev = readw_relaxed(bank->base + bank->regs->revision);  in omap_gpio_show_rev()
1026 static void omap_gpio_mod_init(struct gpio_bank *bank)  in omap_gpio_mod_init()  argument
1028 	void __iomem *base = bank->base;  in omap_gpio_mod_init()
1031 	if (bank->width == 16)  in omap_gpio_mod_init()
1034 	if (bank->is_mpuio) {  in omap_gpio_mod_init()
1035 		writel_relaxed(l, bank->base + bank->regs->irqenable);  in omap_gpio_mod_init()
1039 	omap_gpio_rmw(base, bank->regs->irqenable, l,  in omap_gpio_mod_init()
1040 		      bank->regs->irqenable_inv);  in omap_gpio_mod_init()
1041 	omap_gpio_rmw(base, bank->regs->irqstatus, l,  in omap_gpio_mod_init()
1042 		      !bank->regs->irqenable_inv);  in omap_gpio_mod_init()
1043 	if (bank->regs->debounce_en)  in omap_gpio_mod_init()
1044 		writel_relaxed(0, base + bank->regs->debounce_en);  in omap_gpio_mod_init()
1047 	bank->context.oe = readl_relaxed(bank->base + bank->regs->direction);  in omap_gpio_mod_init()
1049 	if (bank->regs->ctrl)  in omap_gpio_mod_init()
1050 		writel_relaxed(0, base + bank->regs->ctrl);  in omap_gpio_mod_init()
1052 	bank->dbck = clk_get(bank->dev, "dbclk");  in omap_gpio_mod_init()
1053 	if (IS_ERR(bank->dbck))  in omap_gpio_mod_init()
1054 		dev_err(bank->dev, "Could not get gpio dbck\n");  in omap_gpio_mod_init()
1057 static int omap_gpio_chip_init(struct gpio_bank *bank, struct irq_chip *irqc)  in omap_gpio_chip_init()  argument
1067 	bank->chip.request = omap_gpio_request;  in omap_gpio_chip_init()
1068 	bank->chip.free = omap_gpio_free;  in omap_gpio_chip_init()
1069 	bank->chip.get_direction = omap_gpio_get_direction;  in omap_gpio_chip_init()
1070 	bank->chip.direction_input = omap_gpio_input;  in omap_gpio_chip_init()
1071 	bank->chip.get = omap_gpio_get;  in omap_gpio_chip_init()
1072 	bank->chip.direction_output = omap_gpio_output;  in omap_gpio_chip_init()
1073 	bank->chip.set_debounce = omap_gpio_debounce;  in omap_gpio_chip_init()
1074 	bank->chip.set = omap_gpio_set;  in omap_gpio_chip_init()
1075 	if (bank->is_mpuio) {  in omap_gpio_chip_init()
1076 		bank->chip.label = "mpuio";  in omap_gpio_chip_init()
1077 		if (bank->regs->wkup_en)  in omap_gpio_chip_init()
1078 			bank->chip.dev = &omap_mpuio_device.dev;  in omap_gpio_chip_init()
1079 		bank->chip.base = OMAP_MPUIO(0);  in omap_gpio_chip_init()
1081 		bank->chip.label = "gpio";  in omap_gpio_chip_init()
1082 		bank->chip.base = gpio;  in omap_gpio_chip_init()
1083 		gpio += bank->width;  in omap_gpio_chip_init()
1085 	bank->chip.ngpio = bank->width;  in omap_gpio_chip_init()
1087 	ret = gpiochip_add(&bank->chip);  in omap_gpio_chip_init()
1089 		dev_err(bank->dev, "Could not register gpio chip %d\n", ret);  in omap_gpio_chip_init()
1098 	irq_base = irq_alloc_descs(-1, 0, bank->width, 0);  in omap_gpio_chip_init()
1100 		dev_err(bank->dev, "Couldn't allocate IRQ numbers\n");  in omap_gpio_chip_init()
1106 	if (bank->is_mpuio) {  in omap_gpio_chip_init()
1110 		if (!bank->regs->wkup_en)  in omap_gpio_chip_init()
1114 	ret = gpiochip_irqchip_add(&bank->chip, irqc,  in omap_gpio_chip_init()
1119 		dev_err(bank->dev, "Couldn't add irqchip to gpiochip %d\n", ret);  in omap_gpio_chip_init()
1120 		gpiochip_remove(&bank->chip);  in omap_gpio_chip_init()
1124 	gpiochip_set_chained_irqchip(&bank->chip, irqc,  in omap_gpio_chip_init()
1125 				     bank->irq, omap_gpio_irq_handler);  in omap_gpio_chip_init()
1139 	struct gpio_bank *bank;  in omap_gpio_probe()  local
1149 	bank = devm_kzalloc(dev, sizeof(struct gpio_bank), GFP_KERNEL);  in omap_gpio_probe()
1150 	if (!bank) {  in omap_gpio_probe()
1174 	bank->irq = res->start;  in omap_gpio_probe()
1175 	bank->dev = dev;  in omap_gpio_probe()
1176 	bank->chip.dev = dev;  in omap_gpio_probe()
1177 	bank->dbck_flag = pdata->dbck_flag;  in omap_gpio_probe()
1178 	bank->stride = pdata->bank_stride;  in omap_gpio_probe()
1179 	bank->width = pdata->bank_width;  in omap_gpio_probe()
1180 	bank->is_mpuio = pdata->is_mpuio;  in omap_gpio_probe()
1181 	bank->non_wakeup_gpios = pdata->non_wakeup_gpios;  in omap_gpio_probe()
1182 	bank->regs = pdata->regs;  in omap_gpio_probe()
1184 	bank->chip.of_node = of_node_get(node);  in omap_gpio_probe()
1188 			bank->loses_context = true;  in omap_gpio_probe()
1190 		bank->loses_context = pdata->loses_context;  in omap_gpio_probe()
1192 		if (bank->loses_context)  in omap_gpio_probe()
1193 			bank->get_context_loss_count =  in omap_gpio_probe()
1197 	if (bank->regs->set_dataout && bank->regs->clr_dataout)  in omap_gpio_probe()
1198 		bank->set_dataout = omap_set_gpio_dataout_reg;  in omap_gpio_probe()
1200 		bank->set_dataout = omap_set_gpio_dataout_mask;  in omap_gpio_probe()
1202 	spin_lock_init(&bank->lock);  in omap_gpio_probe()
1206 	bank->base = devm_ioremap_resource(dev, res);  in omap_gpio_probe()
1207 	if (IS_ERR(bank->base)) {  in omap_gpio_probe()
1208 		irq_domain_remove(bank->chip.irqdomain);  in omap_gpio_probe()
1209 		return PTR_ERR(bank->base);  in omap_gpio_probe()
1212 	platform_set_drvdata(pdev, bank);  in omap_gpio_probe()
1214 	pm_runtime_enable(bank->dev);  in omap_gpio_probe()
1215 	pm_runtime_irq_safe(bank->dev);  in omap_gpio_probe()
1216 	pm_runtime_get_sync(bank->dev);  in omap_gpio_probe()
1218 	if (bank->is_mpuio)  in omap_gpio_probe()
1219 		omap_mpuio_init(bank);  in omap_gpio_probe()
1221 	omap_gpio_mod_init(bank);  in omap_gpio_probe()
1223 	ret = omap_gpio_chip_init(bank, irqc);  in omap_gpio_probe()
1227 	omap_gpio_show_rev(bank);  in omap_gpio_probe()
1229 	pm_runtime_put(bank->dev);  in omap_gpio_probe()
1231 	list_add_tail(&bank->node, &omap_gpio_list);  in omap_gpio_probe()
1239 static void omap_gpio_restore_context(struct gpio_bank *bank);
1244 	struct gpio_bank *bank = platform_get_drvdata(pdev);  in omap_gpio_runtime_suspend()  local
1249 	spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_runtime_suspend()
1262 	wake_low = bank->context.leveldetect0 & bank->context.wake_en;  in omap_gpio_runtime_suspend()
1264 		writel_relaxed(wake_low | bank->context.fallingdetect,  in omap_gpio_runtime_suspend()
1265 			     bank->base + bank->regs->fallingdetect);  in omap_gpio_runtime_suspend()
1266 	wake_hi = bank->context.leveldetect1 & bank->context.wake_en;  in omap_gpio_runtime_suspend()
1268 		writel_relaxed(wake_hi | bank->context.risingdetect,  in omap_gpio_runtime_suspend()
1269 			     bank->base + bank->regs->risingdetect);  in omap_gpio_runtime_suspend()
1271 	if (!bank->enabled_non_wakeup_gpios)  in omap_gpio_runtime_suspend()
1274 	if (bank->power_mode != OFF_MODE) {  in omap_gpio_runtime_suspend()
1275 		bank->power_mode = 0;  in omap_gpio_runtime_suspend()
1283 	bank->saved_datain = readl_relaxed(bank->base +  in omap_gpio_runtime_suspend()
1284 						bank->regs->datain);  in omap_gpio_runtime_suspend()
1285 	l1 = bank->context.fallingdetect;  in omap_gpio_runtime_suspend()
1286 	l2 = bank->context.risingdetect;  in omap_gpio_runtime_suspend()
1288 	l1 &= ~bank->enabled_non_wakeup_gpios;  in omap_gpio_runtime_suspend()
1289 	l2 &= ~bank->enabled_non_wakeup_gpios;  in omap_gpio_runtime_suspend()
1291 	writel_relaxed(l1, bank->base + bank->regs->fallingdetect);  in omap_gpio_runtime_suspend()
1292 	writel_relaxed(l2, bank->base + bank->regs->risingdetect);  in omap_gpio_runtime_suspend()
1294 	bank->workaround_enabled = true;  in omap_gpio_runtime_suspend()
1297 	if (bank->get_context_loss_count)  in omap_gpio_runtime_suspend()
1298 		bank->context_loss_count =  in omap_gpio_runtime_suspend()
1299 				bank->get_context_loss_count(bank->dev);  in omap_gpio_runtime_suspend()
1301 	omap_gpio_dbck_disable(bank);  in omap_gpio_runtime_suspend()
1302 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_runtime_suspend()
1312 	struct gpio_bank *bank = platform_get_drvdata(pdev);  in omap_gpio_runtime_resume()  local
1317 	spin_lock_irqsave(&bank->lock, flags);  in omap_gpio_runtime_resume()
1324 	if (bank->loses_context && !bank->context_valid) {  in omap_gpio_runtime_resume()
1325 		omap_gpio_init_context(bank);  in omap_gpio_runtime_resume()
1327 		if (bank->get_context_loss_count)  in omap_gpio_runtime_resume()
1328 			bank->context_loss_count =  in omap_gpio_runtime_resume()
1329 				bank->get_context_loss_count(bank->dev);  in omap_gpio_runtime_resume()
1332 	omap_gpio_dbck_enable(bank);  in omap_gpio_runtime_resume()
1340 	writel_relaxed(bank->context.fallingdetect,  in omap_gpio_runtime_resume()
1341 		     bank->base + bank->regs->fallingdetect);  in omap_gpio_runtime_resume()
1342 	writel_relaxed(bank->context.risingdetect,  in omap_gpio_runtime_resume()
1343 		     bank->base + bank->regs->risingdetect);  in omap_gpio_runtime_resume()
1345 	if (bank->loses_context) {  in omap_gpio_runtime_resume()
1346 		if (!bank->get_context_loss_count) {  in omap_gpio_runtime_resume()
1347 			omap_gpio_restore_context(bank);  in omap_gpio_runtime_resume()
1349 			c = bank->get_context_loss_count(bank->dev);  in omap_gpio_runtime_resume()
1350 			if (c != bank->context_loss_count) {  in omap_gpio_runtime_resume()
1351 				omap_gpio_restore_context(bank);  in omap_gpio_runtime_resume()
1353 				spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_runtime_resume()
1359 	if (!bank->workaround_enabled) {  in omap_gpio_runtime_resume()
1360 		spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_runtime_resume()
1364 	l = readl_relaxed(bank->base + bank->regs->datain);  in omap_gpio_runtime_resume()
1372 	l ^= bank->saved_datain;  in omap_gpio_runtime_resume()
1373 	l &= bank->enabled_non_wakeup_gpios;  in omap_gpio_runtime_resume()
1379 	gen0 = l & bank->context.fallingdetect;  in omap_gpio_runtime_resume()
1380 	gen0 &= bank->saved_datain;  in omap_gpio_runtime_resume()
1382 	gen1 = l & bank->context.risingdetect;  in omap_gpio_runtime_resume()
1383 	gen1 &= ~(bank->saved_datain);  in omap_gpio_runtime_resume()
1386 	gen = l & (~(bank->context.fallingdetect) &  in omap_gpio_runtime_resume()
1387 					 ~(bank->context.risingdetect));  in omap_gpio_runtime_resume()
1394 		old0 = readl_relaxed(bank->base + bank->regs->leveldetect0);  in omap_gpio_runtime_resume()
1395 		old1 = readl_relaxed(bank->base + bank->regs->leveldetect1);  in omap_gpio_runtime_resume()
1397 		if (!bank->regs->irqstatus_raw0) {  in omap_gpio_runtime_resume()
1398 			writel_relaxed(old0 | gen, bank->base +  in omap_gpio_runtime_resume()
1399 						bank->regs->leveldetect0);  in omap_gpio_runtime_resume()
1400 			writel_relaxed(old1 | gen, bank->base +  in omap_gpio_runtime_resume()
1401 						bank->regs->leveldetect1);  in omap_gpio_runtime_resume()
1404 		if (bank->regs->irqstatus_raw0) {  in omap_gpio_runtime_resume()
1405 			writel_relaxed(old0 | l, bank->base +  in omap_gpio_runtime_resume()
1406 						bank->regs->leveldetect0);  in omap_gpio_runtime_resume()
1407 			writel_relaxed(old1 | l, bank->base +  in omap_gpio_runtime_resume()
1408 						bank->regs->leveldetect1);  in omap_gpio_runtime_resume()
1410 		writel_relaxed(old0, bank->base + bank->regs->leveldetect0);  in omap_gpio_runtime_resume()
1411 		writel_relaxed(old1, bank->base + bank->regs->leveldetect1);  in omap_gpio_runtime_resume()
1414 	bank->workaround_enabled = false;  in omap_gpio_runtime_resume()
1415 	spin_unlock_irqrestore(&bank->lock, flags);  in omap_gpio_runtime_resume()
1423 	struct gpio_bank *bank;  in omap2_gpio_prepare_for_idle()  local
1425 	list_for_each_entry(bank, &omap_gpio_list, node) {  in omap2_gpio_prepare_for_idle()
1426 		if (!BANK_USED(bank) || !bank->loses_context)  in omap2_gpio_prepare_for_idle()
1429 		bank->power_mode = pwr_mode;  in omap2_gpio_prepare_for_idle()
1431 		pm_runtime_put_sync_suspend(bank->dev);  in omap2_gpio_prepare_for_idle()
1437 	struct gpio_bank *bank;  in omap2_gpio_resume_after_idle()  local
1439 	list_for_each_entry(bank, &omap_gpio_list, node) {  in omap2_gpio_resume_after_idle()
1440 		if (!BANK_USED(bank) || !bank->loses_context)  in omap2_gpio_resume_after_idle()
1443 		pm_runtime_get_sync(bank->dev);  in omap2_gpio_resume_after_idle()
1471 static void omap_gpio_restore_context(struct gpio_bank *bank)  in omap_gpio_restore_context()  argument
1473 	writel_relaxed(bank->context.wake_en,  in omap_gpio_restore_context()
1474 				bank->base + bank->regs->wkup_en);  in omap_gpio_restore_context()
1475 	writel_relaxed(bank->context.ctrl, bank->base + bank->regs->ctrl);  in omap_gpio_restore_context()
1476 	writel_relaxed(bank->context.leveldetect0,  in omap_gpio_restore_context()
1477 				bank->base + bank->regs->leveldetect0);  in omap_gpio_restore_context()
1478 	writel_relaxed(bank->context.leveldetect1,  in omap_gpio_restore_context()
1479 				bank->base + bank->regs->leveldetect1);  in omap_gpio_restore_context()
1480 	writel_relaxed(bank->context.risingdetect,  in omap_gpio_restore_context()
1481 				bank->base + bank->regs->risingdetect);  in omap_gpio_restore_context()
1482 	writel_relaxed(bank->context.fallingdetect,  in omap_gpio_restore_context()
1483 				bank->base + bank->regs->fallingdetect);  in omap_gpio_restore_context()
1484 	if (bank->regs->set_dataout && bank->regs->clr_dataout)  in omap_gpio_restore_context()
1485 		writel_relaxed(bank->context.dataout,  in omap_gpio_restore_context()
1486 				bank->base + bank->regs->set_dataout);  in omap_gpio_restore_context()
1488 		writel_relaxed(bank->context.dataout,  in omap_gpio_restore_context()
1489 				bank->base + bank->regs->dataout);  in omap_gpio_restore_context()
1490 	writel_relaxed(bank->context.oe, bank->base + bank->regs->direction);  in omap_gpio_restore_context()
1492 	if (bank->dbck_enable_mask) {  in omap_gpio_restore_context()
1493 		writel_relaxed(bank->context.debounce, bank->base +  in omap_gpio_restore_context()
1494 					bank->regs->debounce);  in omap_gpio_restore_context()
1495 		writel_relaxed(bank->context.debounce_en,  in omap_gpio_restore_context()
1496 					bank->base + bank->regs->debounce_en);  in omap_gpio_restore_context()
1499 	writel_relaxed(bank->context.irqenable1,  in omap_gpio_restore_context()
1500 				bank->base + bank->regs->irqenable);  in omap_gpio_restore_context()
1501 	writel_relaxed(bank->context.irqenable2,  in omap_gpio_restore_context()
1502 				bank->base + bank->regs->irqenable2);  in omap_gpio_restore_context()