Lines Matching refs:dcrtc
91 armada_drm_crtc_update_regs(struct armada_crtc *dcrtc, struct armada_regs *regs) in armada_drm_crtc_update_regs() argument
94 void __iomem *reg = dcrtc->base + regs->offset; in armada_drm_crtc_update_regs()
107 static void armada_drm_crtc_update(struct armada_crtc *dcrtc) in armada_drm_crtc_update() argument
111 dumb_ctrl = dcrtc->cfg_dumb_ctrl; in armada_drm_crtc_update()
113 if (!dpms_blanked(dcrtc->dpms)) in armada_drm_crtc_update()
122 if (dpms_blanked(dcrtc->dpms) && in armada_drm_crtc_update()
136 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NCSYNC) in armada_drm_crtc_update()
138 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NHSYNC) in armada_drm_crtc_update()
140 if (dcrtc->crtc.mode.flags & DRM_MODE_FLAG_NVSYNC) in armada_drm_crtc_update()
143 if (dcrtc->dumb_ctrl != dumb_ctrl) { in armada_drm_crtc_update()
144 dcrtc->dumb_ctrl = dumb_ctrl; in armada_drm_crtc_update()
145 writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL); in armada_drm_crtc_update()
176 static int armada_drm_crtc_queue_frame_work(struct armada_crtc *dcrtc, in armada_drm_crtc_queue_frame_work() argument
179 struct drm_device *dev = dcrtc->crtc.dev; in armada_drm_crtc_queue_frame_work()
183 ret = drm_vblank_get(dev, dcrtc->num); in armada_drm_crtc_queue_frame_work()
190 if (!dcrtc->frame_work) in armada_drm_crtc_queue_frame_work()
191 dcrtc->frame_work = work; in armada_drm_crtc_queue_frame_work()
197 drm_vblank_put(dev, dcrtc->num); in armada_drm_crtc_queue_frame_work()
202 static void armada_drm_crtc_complete_frame_work(struct armada_crtc *dcrtc) in armada_drm_crtc_complete_frame_work() argument
204 struct drm_device *dev = dcrtc->crtc.dev; in armada_drm_crtc_complete_frame_work()
205 struct armada_frame_work *work = dcrtc->frame_work; in armada_drm_crtc_complete_frame_work()
207 dcrtc->frame_work = NULL; in armada_drm_crtc_complete_frame_work()
209 armada_drm_crtc_update_regs(dcrtc, work->regs); in armada_drm_crtc_complete_frame_work()
212 drm_send_vblank_event(dev, dcrtc->num, work->event); in armada_drm_crtc_complete_frame_work()
214 drm_vblank_put(dev, dcrtc->num); in armada_drm_crtc_complete_frame_work()
217 __armada_drm_queue_unref_work(dcrtc->crtc.dev, work->old_fb); in armada_drm_crtc_complete_frame_work()
221 static void armada_drm_crtc_finish_fb(struct armada_crtc *dcrtc, in armada_drm_crtc_finish_fb() argument
242 if (armada_drm_crtc_queue_frame_work(dcrtc, work) == 0) in armada_drm_crtc_finish_fb()
256 static void armada_drm_vblank_off(struct armada_crtc *dcrtc) in armada_drm_vblank_off() argument
258 struct drm_device *dev = dcrtc->crtc.dev; in armada_drm_vblank_off()
264 drm_crtc_vblank_off(&dcrtc->crtc); in armada_drm_vblank_off()
268 if (dcrtc->frame_work) in armada_drm_vblank_off()
269 armada_drm_crtc_complete_frame_work(dcrtc); in armada_drm_vblank_off()
286 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_dpms() local
288 if (dcrtc->dpms != dpms) { in armada_drm_crtc_dpms()
289 dcrtc->dpms = dpms; in armada_drm_crtc_dpms()
290 armada_drm_crtc_update(dcrtc); in armada_drm_crtc_dpms()
292 armada_drm_vblank_off(dcrtc); in armada_drm_crtc_dpms()
294 drm_crtc_vblank_on(&dcrtc->crtc); in armada_drm_crtc_dpms()
307 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_prepare() local
315 plane = dcrtc->plane; in armada_drm_crtc_prepare()
329 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_commit() local
331 if (dcrtc->dpms != DRM_MODE_DPMS_ON) { in armada_drm_crtc_commit()
332 dcrtc->dpms = DRM_MODE_DPMS_ON; in armada_drm_crtc_commit()
333 armada_drm_crtc_update(dcrtc); in armada_drm_crtc_commit()
341 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_mode_fixup() local
345 if (!dcrtc->variant->has_spu_adv_reg && in armada_drm_crtc_mode_fixup()
350 ret = dcrtc->variant->compute_clock(dcrtc, adj, NULL); in armada_drm_crtc_mode_fixup()
357 static void armada_drm_crtc_irq(struct armada_crtc *dcrtc, u32 stat) in armada_drm_crtc_irq() argument
360 void __iomem *base = dcrtc->base; in armada_drm_crtc_irq()
363 DRM_ERROR("video underflow on crtc %u\n", dcrtc->num); in armada_drm_crtc_irq()
365 DRM_ERROR("graphics underflow on crtc %u\n", dcrtc->num); in armada_drm_crtc_irq()
368 drm_handle_vblank(dcrtc->crtc.dev, dcrtc->num); in armada_drm_crtc_irq()
370 spin_lock(&dcrtc->irq_lock); in armada_drm_crtc_irq()
372 list_for_each_entry_safe(e, n, &dcrtc->vbl_list, node) { in armada_drm_crtc_irq()
374 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); in armada_drm_crtc_irq()
375 e->fn(dcrtc, e->data); in armada_drm_crtc_irq()
378 if (stat & GRA_FRAME_IRQ && dcrtc->interlaced) { in armada_drm_crtc_irq()
382 writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH); in armada_drm_crtc_irq()
383 writel_relaxed(dcrtc->v[i].spu_v_h_total, in armada_drm_crtc_irq()
388 val |= dcrtc->v[i].spu_adv_reg; in armada_drm_crtc_irq()
392 if (stat & DUMB_FRAMEDONE && dcrtc->cursor_update) { in armada_drm_crtc_irq()
393 writel_relaxed(dcrtc->cursor_hw_pos, in armada_drm_crtc_irq()
395 writel_relaxed(dcrtc->cursor_hw_sz, in armada_drm_crtc_irq()
400 dcrtc->cursor_update = false; in armada_drm_crtc_irq()
401 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); in armada_drm_crtc_irq()
404 spin_unlock(&dcrtc->irq_lock); in armada_drm_crtc_irq()
407 struct drm_device *dev = dcrtc->crtc.dev; in armada_drm_crtc_irq()
410 if (dcrtc->frame_work) in armada_drm_crtc_irq()
411 armada_drm_crtc_complete_frame_work(dcrtc); in armada_drm_crtc_irq()
414 wake_up(&dcrtc->frame_wait); in armada_drm_crtc_irq()
420 struct armada_crtc *dcrtc = arg; in armada_drm_irq() local
421 u32 v, stat = readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_irq()
427 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_irq()
430 v = stat & dcrtc->irq_ena; in armada_drm_irq()
433 armada_drm_crtc_irq(dcrtc, stat); in armada_drm_irq()
440 void armada_drm_crtc_disable_irq(struct armada_crtc *dcrtc, u32 mask) in armada_drm_crtc_disable_irq() argument
442 if (dcrtc->irq_ena & mask) { in armada_drm_crtc_disable_irq()
443 dcrtc->irq_ena &= ~mask; in armada_drm_crtc_disable_irq()
444 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_disable_irq()
448 void armada_drm_crtc_enable_irq(struct armada_crtc *dcrtc, u32 mask) in armada_drm_crtc_enable_irq() argument
450 if ((dcrtc->irq_ena & mask) != mask) { in armada_drm_crtc_enable_irq()
451 dcrtc->irq_ena |= mask; in armada_drm_crtc_enable_irq()
452 writel(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_enable_irq()
453 if (readl_relaxed(dcrtc->base + LCD_SPU_IRQ_ISR) & mask) in armada_drm_crtc_enable_irq()
454 writel(0, dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_crtc_enable_irq()
458 static uint32_t armada_drm_crtc_calculate_csc(struct armada_crtc *dcrtc) in armada_drm_crtc_calculate_csc() argument
460 struct drm_display_mode *adj = &dcrtc->crtc.mode; in armada_drm_crtc_calculate_csc()
463 if (dcrtc->csc_yuv_mode == CSC_YUV_CCIR709) in armada_drm_crtc_calculate_csc()
465 if (dcrtc->csc_rgb_mode == CSC_RGB_STUDIO) in armada_drm_crtc_calculate_csc()
478 if (dcrtc->csc_yuv_mode == CSC_AUTO) in armada_drm_crtc_calculate_csc()
488 if (dcrtc->csc_rgb_mode == CSC_AUTO) in armada_drm_crtc_calculate_csc()
499 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_mode_set() local
510 i = armada_drm_crtc_calc_fb(dcrtc->crtc.primary->fb, in armada_drm_crtc_mode_set()
530 wait_event(dcrtc->frame_wait, !dcrtc->frame_work); in armada_drm_crtc_mode_set()
536 val = dcrtc->dumb_ctrl & ~CFG_DUMB_ENA; in armada_drm_crtc_mode_set()
537 if (val != dcrtc->dumb_ctrl) { in armada_drm_crtc_mode_set()
538 dcrtc->dumb_ctrl = val; in armada_drm_crtc_mode_set()
539 writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL); in armada_drm_crtc_mode_set()
543 dcrtc->variant->compute_clock(dcrtc, adj, &sclk); in armada_drm_crtc_mode_set()
549 if (interlaced ^ dcrtc->interlaced) { in armada_drm_crtc_mode_set()
551 drm_vblank_get(dcrtc->crtc.dev, dcrtc->num); in armada_drm_crtc_mode_set()
553 drm_vblank_put(dcrtc->crtc.dev, dcrtc->num); in armada_drm_crtc_mode_set()
554 dcrtc->interlaced = interlaced; in armada_drm_crtc_mode_set()
557 spin_lock_irqsave(&dcrtc->irq_lock, flags); in armada_drm_crtc_mode_set()
560 dcrtc->v[1].spu_v_h_total = adj->crtc_vtotal << 16 | in armada_drm_crtc_mode_set()
562 dcrtc->v[1].spu_v_porch = tm << 16 | bm; in armada_drm_crtc_mode_set()
564 dcrtc->v[1].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN | in armada_drm_crtc_mode_set()
565 dcrtc->variant->spu_adv_reg; in armada_drm_crtc_mode_set()
569 dcrtc->v[0].spu_v_h_total = dcrtc->v[1].spu_v_h_total + in armada_drm_crtc_mode_set()
571 dcrtc->v[0].spu_v_porch = dcrtc->v[1].spu_v_porch + 1; in armada_drm_crtc_mode_set()
573 dcrtc->v[0].spu_adv_reg = val << 20 | val | ADV_VSYNCOFFEN | in armada_drm_crtc_mode_set()
574 dcrtc->variant->spu_adv_reg; in armada_drm_crtc_mode_set()
576 dcrtc->v[0] = dcrtc->v[1]; in armada_drm_crtc_mode_set()
585 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_porch, LCD_SPU_V_PORCH); in armada_drm_crtc_mode_set()
586 armada_reg_queue_set(regs, i, dcrtc->v[0].spu_v_h_total, in armada_drm_crtc_mode_set()
589 if (dcrtc->variant->has_spu_adv_reg) { in armada_drm_crtc_mode_set()
590 armada_reg_queue_mod(regs, i, dcrtc->v[0].spu_adv_reg, in armada_drm_crtc_mode_set()
596 val |= CFG_GRA_FMT(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt); in armada_drm_crtc_mode_set()
597 val |= CFG_GRA_MOD(drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->mod); in armada_drm_crtc_mode_set()
599 if (drm_fb_to_armada_fb(dcrtc->crtc.primary->fb)->fmt > CFG_420) in armada_drm_crtc_mode_set()
614 val = dcrtc->spu_iopad_ctrl | armada_drm_crtc_calculate_csc(dcrtc); in armada_drm_crtc_mode_set()
618 armada_drm_crtc_update_regs(dcrtc, regs); in armada_drm_crtc_mode_set()
619 spin_unlock_irqrestore(&dcrtc->irq_lock, flags); in armada_drm_crtc_mode_set()
621 armada_drm_crtc_update(dcrtc); in armada_drm_crtc_mode_set()
624 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms)); in armada_drm_crtc_mode_set()
633 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_mode_set_base() local
638 dcrtc->interlaced); in armada_drm_crtc_mode_set_base()
642 wait_event(dcrtc->frame_wait, !dcrtc->frame_work); in armada_drm_crtc_mode_set_base()
648 armada_drm_crtc_update_regs(dcrtc, regs); in armada_drm_crtc_mode_set_base()
651 armada_drm_crtc_finish_fb(dcrtc, old_fb, dpms_blanked(dcrtc->dpms)); in armada_drm_crtc_mode_set_base()
659 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_disable() local
662 armada_drm_crtc_finish_fb(dcrtc, crtc->primary->fb, true); in armada_drm_crtc_disable()
667 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); in armada_drm_crtc_disable()
724 static int armada_drm_crtc_cursor_update(struct armada_crtc *dcrtc, bool reload) in armada_drm_crtc_cursor_update() argument
726 uint32_t xoff, xscr, w = dcrtc->cursor_w, s; in armada_drm_crtc_cursor_update()
727 uint32_t yoff, yscr, h = dcrtc->cursor_h; in armada_drm_crtc_cursor_update()
734 if (dcrtc->cursor_x < 0) { in armada_drm_crtc_cursor_update()
735 xoff = -dcrtc->cursor_x; in armada_drm_crtc_cursor_update()
738 } else if (dcrtc->cursor_x + w > dcrtc->crtc.mode.hdisplay) { in armada_drm_crtc_cursor_update()
740 xscr = dcrtc->cursor_x; in armada_drm_crtc_cursor_update()
741 w = max_t(int, dcrtc->crtc.mode.hdisplay - dcrtc->cursor_x, 0); in armada_drm_crtc_cursor_update()
744 xscr = dcrtc->cursor_x; in armada_drm_crtc_cursor_update()
747 if (dcrtc->cursor_y < 0) { in armada_drm_crtc_cursor_update()
748 yoff = -dcrtc->cursor_y; in armada_drm_crtc_cursor_update()
751 } else if (dcrtc->cursor_y + h > dcrtc->crtc.mode.vdisplay) { in armada_drm_crtc_cursor_update()
753 yscr = dcrtc->cursor_y; in armada_drm_crtc_cursor_update()
754 h = max_t(int, dcrtc->crtc.mode.vdisplay - dcrtc->cursor_y, 0); in armada_drm_crtc_cursor_update()
757 yscr = dcrtc->cursor_y; in armada_drm_crtc_cursor_update()
761 s = dcrtc->cursor_w; in armada_drm_crtc_cursor_update()
762 if (dcrtc->interlaced) { in armada_drm_crtc_cursor_update()
768 if (!dcrtc->cursor_obj || !h || !w) { in armada_drm_crtc_cursor_update()
769 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
770 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); in armada_drm_crtc_cursor_update()
771 dcrtc->cursor_update = false; in armada_drm_crtc_cursor_update()
772 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); in armada_drm_crtc_cursor_update()
773 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
777 para1 = readl_relaxed(dcrtc->base + LCD_SPU_SRAM_PARA1); in armada_drm_crtc_cursor_update()
779 dcrtc->base + LCD_SPU_SRAM_PARA1); in armada_drm_crtc_cursor_update()
786 armada_drm_crtc_cursor_tran(dcrtc->base); in armada_drm_crtc_cursor_update()
790 if (dcrtc->cursor_hw_sz != (h << 16 | w)) { in armada_drm_crtc_cursor_update()
791 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
792 armada_drm_crtc_disable_irq(dcrtc, DUMB_FRAMEDONE_ENA); in armada_drm_crtc_cursor_update()
793 dcrtc->cursor_update = false; in armada_drm_crtc_cursor_update()
794 armada_updatel(0, CFG_HWC_ENA, dcrtc->base + LCD_SPU_DMA_CTRL0); in armada_drm_crtc_cursor_update()
795 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
799 struct armada_gem_object *obj = dcrtc->cursor_obj; in armada_drm_crtc_cursor_update()
804 armada_load_cursor_argb(dcrtc->base, pix, s, w, h); in armada_drm_crtc_cursor_update()
808 spin_lock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
809 dcrtc->cursor_hw_pos = yscr << 16 | xscr; in armada_drm_crtc_cursor_update()
810 dcrtc->cursor_hw_sz = h << 16 | w; in armada_drm_crtc_cursor_update()
811 dcrtc->cursor_update = true; in armada_drm_crtc_cursor_update()
812 armada_drm_crtc_enable_irq(dcrtc, DUMB_FRAMEDONE_ENA); in armada_drm_crtc_cursor_update()
813 spin_unlock_irq(&dcrtc->irq_lock); in armada_drm_crtc_cursor_update()
827 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_cursor_set() local
832 if (!dcrtc->variant->has_spu_adv_reg) in armada_drm_crtc_cursor_set()
858 if (dcrtc->cursor_obj) { in armada_drm_crtc_cursor_set()
859 dcrtc->cursor_obj->update = NULL; in armada_drm_crtc_cursor_set()
860 dcrtc->cursor_obj->update_data = NULL; in armada_drm_crtc_cursor_set()
861 drm_gem_object_unreference(&dcrtc->cursor_obj->obj); in armada_drm_crtc_cursor_set()
863 dcrtc->cursor_obj = obj; in armada_drm_crtc_cursor_set()
864 dcrtc->cursor_w = w; in armada_drm_crtc_cursor_set()
865 dcrtc->cursor_h = h; in armada_drm_crtc_cursor_set()
866 ret = armada_drm_crtc_cursor_update(dcrtc, true); in armada_drm_crtc_cursor_set()
868 obj->update_data = dcrtc; in armada_drm_crtc_cursor_set()
879 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_cursor_move() local
883 if (!dcrtc->variant->has_spu_adv_reg) in armada_drm_crtc_cursor_move()
887 dcrtc->cursor_x = x; in armada_drm_crtc_cursor_move()
888 dcrtc->cursor_y = y; in armada_drm_crtc_cursor_move()
889 ret = armada_drm_crtc_cursor_update(dcrtc, false); in armada_drm_crtc_cursor_move()
897 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_destroy() local
900 if (dcrtc->cursor_obj) in armada_drm_crtc_destroy()
901 drm_gem_object_unreference(&dcrtc->cursor_obj->obj); in armada_drm_crtc_destroy()
903 priv->dcrtc[dcrtc->num] = NULL; in armada_drm_crtc_destroy()
904 drm_crtc_cleanup(&dcrtc->crtc); in armada_drm_crtc_destroy()
906 if (!IS_ERR(dcrtc->clk)) in armada_drm_crtc_destroy()
907 clk_disable_unprepare(dcrtc->clk); in armada_drm_crtc_destroy()
909 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_destroy()
911 of_node_put(dcrtc->crtc.port); in armada_drm_crtc_destroy()
913 kfree(dcrtc); in armada_drm_crtc_destroy()
923 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_page_flip() local
939 work->old_fb = dcrtc->crtc.primary->fb; in armada_drm_crtc_page_flip()
942 dcrtc->interlaced); in armada_drm_crtc_page_flip()
951 ret = armada_drm_crtc_queue_frame_work(dcrtc, work); in armada_drm_crtc_page_flip()
965 dcrtc->crtc.primary->fb = fb; in armada_drm_crtc_page_flip()
971 if (dpms_blanked(dcrtc->dpms)) { in armada_drm_crtc_page_flip()
973 if (dcrtc->frame_work) in armada_drm_crtc_page_flip()
974 armada_drm_crtc_complete_frame_work(dcrtc); in armada_drm_crtc_page_flip()
986 struct armada_crtc *dcrtc = drm_to_armada_crtc(crtc); in armada_drm_crtc_set_property() local
990 dcrtc->csc_yuv_mode = val; in armada_drm_crtc_set_property()
993 dcrtc->csc_rgb_mode = val; in armada_drm_crtc_set_property()
1000 val = dcrtc->spu_iopad_ctrl | in armada_drm_crtc_set_property()
1001 armada_drm_crtc_calculate_csc(dcrtc); in armada_drm_crtc_set_property()
1002 writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL); in armada_drm_crtc_set_property()
1054 struct armada_crtc *dcrtc; in armada_drm_crtc_create() local
1066 dcrtc = kzalloc(sizeof(*dcrtc), GFP_KERNEL); in armada_drm_crtc_create()
1067 if (!dcrtc) { in armada_drm_crtc_create()
1073 dev_set_drvdata(dev, dcrtc); in armada_drm_crtc_create()
1075 dcrtc->variant = variant; in armada_drm_crtc_create()
1076 dcrtc->base = base; in armada_drm_crtc_create()
1077 dcrtc->num = drm->mode_config.num_crtc; in armada_drm_crtc_create()
1078 dcrtc->clk = ERR_PTR(-EINVAL); in armada_drm_crtc_create()
1079 dcrtc->csc_yuv_mode = CSC_AUTO; in armada_drm_crtc_create()
1080 dcrtc->csc_rgb_mode = CSC_AUTO; in armada_drm_crtc_create()
1081 dcrtc->cfg_dumb_ctrl = DUMB24_RGB888_0; in armada_drm_crtc_create()
1082 dcrtc->spu_iopad_ctrl = CFG_VSCALE_LN_EN | CFG_IOPAD_DUMB24; in armada_drm_crtc_create()
1083 spin_lock_init(&dcrtc->irq_lock); in armada_drm_crtc_create()
1084 dcrtc->irq_ena = CLEAN_SPU_IRQ_ISR; in armada_drm_crtc_create()
1085 INIT_LIST_HEAD(&dcrtc->vbl_list); in armada_drm_crtc_create()
1086 init_waitqueue_head(&dcrtc->frame_wait); in armada_drm_crtc_create()
1089 writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV); in armada_drm_crtc_create()
1090 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR); in armada_drm_crtc_create()
1091 writel_relaxed(dcrtc->spu_iopad_ctrl, in armada_drm_crtc_create()
1092 dcrtc->base + LCD_SPU_IOPAD_CONTROL); in armada_drm_crtc_create()
1093 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0); in armada_drm_crtc_create()
1096 CFG_PDWN64x66, dcrtc->base + LCD_SPU_SRAM_PARA1); in armada_drm_crtc_create()
1097 writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1); in armada_drm_crtc_create()
1098 writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN); in armada_drm_crtc_create()
1099 writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA); in armada_drm_crtc_create()
1100 writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR); in armada_drm_crtc_create()
1103 dcrtc); in armada_drm_crtc_create()
1105 kfree(dcrtc); in armada_drm_crtc_create()
1109 if (dcrtc->variant->init) { in armada_drm_crtc_create()
1110 ret = dcrtc->variant->init(dcrtc, dev); in armada_drm_crtc_create()
1112 kfree(dcrtc); in armada_drm_crtc_create()
1118 armada_updatel(CFG_ARBFAST_ENA, 0, dcrtc->base + LCD_SPU_DMA_CTRL0); in armada_drm_crtc_create()
1120 priv->dcrtc[dcrtc->num] = dcrtc; in armada_drm_crtc_create()
1122 dcrtc->crtc.port = port; in armada_drm_crtc_create()
1123 drm_crtc_init(drm, &dcrtc->crtc, &armada_crtc_funcs); in armada_drm_crtc_create()
1124 drm_crtc_helper_add(&dcrtc->crtc, &armada_crtc_helper_funcs); in armada_drm_crtc_create()
1126 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_yuv_prop, in armada_drm_crtc_create()
1127 dcrtc->csc_yuv_mode); in armada_drm_crtc_create()
1128 drm_object_attach_property(&dcrtc->crtc.base, priv->csc_rgb_prop, in armada_drm_crtc_create()
1129 dcrtc->csc_rgb_mode); in armada_drm_crtc_create()
1131 return armada_overlay_plane_create(drm, 1 << dcrtc->num); in armada_drm_crtc_create()
1183 struct armada_crtc *dcrtc = dev_get_drvdata(dev); in armada_lcd_unbind() local
1185 armada_drm_crtc_destroy(&dcrtc->crtc); in armada_lcd_unbind()