100 		writel_relaxed(val | regs->val, reg);  in armada_drm_crtc_update_regs()
145 		writel_relaxed(dumb_ctrl, dcrtc->base + LCD_SPU_DUMB_CTRL);  in armada_drm_crtc_update()
382 		writel_relaxed(dcrtc->v[i].spu_v_porch, base + LCD_SPU_V_PORCH);  in armada_drm_crtc_irq()
383 		writel_relaxed(dcrtc->v[i].spu_v_h_total,  in armada_drm_crtc_irq()
389 		writel_relaxed(val, base + LCD_SPU_ADV_REG);  in armada_drm_crtc_irq()
393 		writel_relaxed(dcrtc->cursor_hw_pos,  in armada_drm_crtc_irq()
395 		writel_relaxed(dcrtc->cursor_hw_sz,  in armada_drm_crtc_irq()
427 	writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);  in armada_drm_irq()
539 		writel_relaxed(val, dcrtc->base + LCD_SPU_DUMB_CTRL);  in armada_drm_crtc_mode_set()
665 	writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |  in armada_drm_crtc_disable()
698 			writel_relaxed(val,  in armada_load_cursor_argb()
700 			writel_relaxed(addr | SRAM_WRITE,  in armada_load_cursor_argb()
718 		writel_relaxed(0x55555555, base + LCD_SPU_SRAM_WRDAT);  in armada_drm_crtc_cursor_tran()
719 		writel_relaxed(addr | SRAM_WRITE | SRAM_HWC32_TRAN,  in armada_drm_crtc_cursor_tran()
909 	writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ENA);  in armada_drm_crtc_destroy()
1002 		writel_relaxed(val, dcrtc->base + LCD_SPU_IOPAD_CONTROL);  in armada_drm_crtc_set_property()
1089 	writel_relaxed(0x00000001, dcrtc->base + LCD_CFG_SCLK_DIV);  in armada_drm_crtc_create()
1090 	writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_BLANKCOLOR);  in armada_drm_crtc_create()
1091 	writel_relaxed(dcrtc->spu_iopad_ctrl,  in armada_drm_crtc_create()
1093 	writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_SRAM_PARA0);  in armada_drm_crtc_create()
1094 	writel_relaxed(CFG_PDWN256x32 | CFG_PDWN256x24 | CFG_PDWN256x8 |  in armada_drm_crtc_create()
1097 	writel_relaxed(0x2032ff81, dcrtc->base + LCD_SPU_DMA_CTRL1);  in armada_drm_crtc_create()
1098 	writel_relaxed(0x00000000, dcrtc->base + LCD_SPU_GRA_OVSA_HPXL_VLN);  in armada_drm_crtc_create()
1099 	writel_relaxed(dcrtc->irq_ena, dcrtc->base + LCD_SPU_IRQ_ENA);  in armada_drm_crtc_create()
1100 	writel_relaxed(0, dcrtc->base + LCD_SPU_IRQ_ISR);  in armada_drm_crtc_create()