Lines Matching refs:val
221 u32 val = readl(ctx->regs + WINCON(win)); in fimd_enable_video_output() local
224 val |= WINCONx_ENWIN; in fimd_enable_video_output()
226 val &= ~WINCONx_ENWIN; in fimd_enable_video_output()
228 writel(val, ctx->regs + WINCON(win)); in fimd_enable_video_output()
235 u32 val = readl(ctx->regs + SHADOWCON); in fimd_enable_shadow_channel_path() local
238 val |= SHADOWCON_CHx_ENABLE(win); in fimd_enable_shadow_channel_path()
240 val &= ~SHADOWCON_CHx_ENABLE(win); in fimd_enable_shadow_channel_path()
242 writel(val, ctx->regs + SHADOWCON); in fimd_enable_shadow_channel_path()
253 u32 val = readl(ctx->regs + WINCON(win)); in fimd_clear_channel() local
255 if (val & WINCONx_ENWIN) { in fimd_clear_channel()
343 u32 val, clkdiv; in fimd_commit() local
353 val = ctx->i80ifcon | I80IFEN_ENABLE; in fimd_commit()
354 writel(val, timing_base + I80IFCONFAx(0)); in fimd_commit()
385 val = VIDTCON0_VBPD(vbpd - 1) | in fimd_commit()
388 writel(val, ctx->regs + driver_data->timing_base + VIDTCON0); in fimd_commit()
395 val = VIDTCON1_HBPD(hbpd - 1) | in fimd_commit()
398 writel(val, ctx->regs + driver_data->timing_base + VIDTCON1); in fimd_commit()
414 val = VIDTCON2_LINEVAL(mode->vdisplay - 1) | in fimd_commit()
418 writel(val, ctx->regs + driver_data->timing_base + VIDTCON2); in fimd_commit()
424 val = ctx->vidcon0; in fimd_commit()
425 val |= VIDCON0_ENVID | VIDCON0_ENVID_F; in fimd_commit()
428 val |= VIDCON0_CLKSEL_LCD; in fimd_commit()
432 val |= VIDCON0_CLKVAL_F(clkdiv - 1) | VIDCON0_CLKDIR; in fimd_commit()
434 writel(val, ctx->regs + VIDCON0); in fimd_commit()
440 u32 val; in fimd_enable_vblank() local
446 val = readl(ctx->regs + VIDINTCON0); in fimd_enable_vblank()
448 val |= VIDINTCON0_INT_ENABLE; in fimd_enable_vblank()
451 val |= VIDINTCON0_INT_I80IFDONE; in fimd_enable_vblank()
452 val |= VIDINTCON0_INT_SYSMAINCON; in fimd_enable_vblank()
453 val &= ~VIDINTCON0_INT_SYSSUBCON; in fimd_enable_vblank()
455 val |= VIDINTCON0_INT_FRAME; in fimd_enable_vblank()
457 val &= ~VIDINTCON0_FRAMESEL0_MASK; in fimd_enable_vblank()
458 val |= VIDINTCON0_FRAMESEL0_VSYNC; in fimd_enable_vblank()
459 val &= ~VIDINTCON0_FRAMESEL1_MASK; in fimd_enable_vblank()
460 val |= VIDINTCON0_FRAMESEL1_NONE; in fimd_enable_vblank()
463 writel(val, ctx->regs + VIDINTCON0); in fimd_enable_vblank()
472 u32 val; in fimd_disable_vblank() local
478 val = readl(ctx->regs + VIDINTCON0); in fimd_disable_vblank()
480 val &= ~VIDINTCON0_INT_ENABLE; in fimd_disable_vblank()
483 val &= ~VIDINTCON0_INT_I80IFDONE; in fimd_disable_vblank()
484 val &= ~VIDINTCON0_INT_SYSMAINCON; in fimd_disable_vblank()
485 val &= ~VIDINTCON0_INT_SYSSUBCON; in fimd_disable_vblank()
487 val &= ~VIDINTCON0_INT_FRAME; in fimd_disable_vblank()
489 writel(val, ctx->regs + VIDINTCON0); in fimd_disable_vblank()
496 unsigned long val; in fimd_win_set_pixfmt() local
498 val = WINCONx_ENWIN; in fimd_win_set_pixfmt()
511 val |= WINCON0_BPPMODE_8BPP_PALETTE; in fimd_win_set_pixfmt()
512 val |= WINCONx_BURSTLEN_8WORD; in fimd_win_set_pixfmt()
513 val |= WINCONx_BYTSWP; in fimd_win_set_pixfmt()
516 val |= WINCON0_BPPMODE_16BPP_1555; in fimd_win_set_pixfmt()
517 val |= WINCONx_HAWSWP; in fimd_win_set_pixfmt()
518 val |= WINCONx_BURSTLEN_16WORD; in fimd_win_set_pixfmt()
521 val |= WINCON0_BPPMODE_16BPP_565; in fimd_win_set_pixfmt()
522 val |= WINCONx_HAWSWP; in fimd_win_set_pixfmt()
523 val |= WINCONx_BURSTLEN_16WORD; in fimd_win_set_pixfmt()
526 val |= WINCON0_BPPMODE_24BPP_888; in fimd_win_set_pixfmt()
527 val |= WINCONx_WSWP; in fimd_win_set_pixfmt()
528 val |= WINCONx_BURSTLEN_16WORD; in fimd_win_set_pixfmt()
531 val |= WINCON1_BPPMODE_25BPP_A1888 in fimd_win_set_pixfmt()
533 val |= WINCONx_WSWP; in fimd_win_set_pixfmt()
534 val |= WINCONx_BURSTLEN_16WORD; in fimd_win_set_pixfmt()
539 val |= WINCON0_BPPMODE_24BPP_888; in fimd_win_set_pixfmt()
540 val |= WINCONx_WSWP; in fimd_win_set_pixfmt()
541 val |= WINCONx_BURSTLEN_16WORD; in fimd_win_set_pixfmt()
556 val &= ~WINCONx_BURSTLEN_MASK; in fimd_win_set_pixfmt()
557 val |= WINCONx_BURSTLEN_4WORD; in fimd_win_set_pixfmt()
560 writel(val, ctx->regs + WINCON(win)); in fimd_win_set_pixfmt()
565 val = VIDISD14C_ALPHA0_R(0xf) | in fimd_win_set_pixfmt()
572 writel(val, ctx->regs + VIDOSD_C(win)); in fimd_win_set_pixfmt()
574 val = VIDW_ALPHA_R(0xf) | VIDW_ALPHA_G(0xf) | in fimd_win_set_pixfmt()
576 writel(val, ctx->regs + VIDWnALPHA0(win)); in fimd_win_set_pixfmt()
577 writel(val, ctx->regs + VIDWnALPHA1(win)); in fimd_win_set_pixfmt()
603 u32 reg, bits, val; in fimd_shadow_protect_win() local
613 val = readl(ctx->regs + reg); in fimd_shadow_protect_win()
615 val |= bits; in fimd_shadow_protect_win()
617 val &= ~bits; in fimd_shadow_protect_win()
618 writel(val, ctx->regs + reg); in fimd_shadow_protect_win()
626 unsigned long val, size, offset; in fimd_win_commit() local
662 val = (unsigned long)dma_addr; in fimd_win_commit()
663 writel(val, ctx->regs + VIDWx_BUF_START(win, 0)); in fimd_win_commit()
667 val = (unsigned long)(dma_addr + size); in fimd_win_commit()
668 writel(val, ctx->regs + VIDWx_BUF_END(win, 0)); in fimd_win_commit()
671 (unsigned long)dma_addr, val, size); in fimd_win_commit()
678 val = VIDW_BUF_SIZE_OFFSET(buf_offsize) | in fimd_win_commit()
682 writel(val, ctx->regs + VIDWx_BUF_SIZE(win, 0)); in fimd_win_commit()
685 val = VIDOSDxA_TOPLEFT_X(plane->crtc_x) | in fimd_win_commit()
689 writel(val, ctx->regs + VIDOSD_A(win)); in fimd_win_commit()
698 val = VIDOSDxB_BOTRIGHT_X(last_x) | VIDOSDxB_BOTRIGHT_Y(last_y) | in fimd_win_commit()
701 writel(val, ctx->regs + VIDOSD_B(win)); in fimd_win_commit()
711 val = plane->crtc_width * plane->crtc_height; in fimd_win_commit()
712 writel(val, ctx->regs + offset); in fimd_win_commit()
714 DRM_DEBUG_KMS("osd size = 0x%x\n", (unsigned int)val); in fimd_win_commit()
952 u32 val; in fimd_dp_clock_enable() local
962 val = enable ? DP_MIE_CLK_DP_ENABLE : DP_MIE_CLK_DISABLE; in fimd_dp_clock_enable()
982 u32 val, clear_bit; in fimd_irq_handler() local
984 val = readl(ctx->regs + VIDINTCON1); in fimd_irq_handler()
987 if (val & clear_bit) in fimd_irq_handler()
1098 u32 val; in fimd_probe() local
1112 if (of_property_read_u32(i80_if_timings, "cs-setup", &val)) in fimd_probe()
1113 val = 0; in fimd_probe()
1114 ctx->i80ifcon = LCD_CS_SETUP(val); in fimd_probe()
1115 if (of_property_read_u32(i80_if_timings, "wr-setup", &val)) in fimd_probe()
1116 val = 0; in fimd_probe()
1117 ctx->i80ifcon |= LCD_WR_SETUP(val); in fimd_probe()
1118 if (of_property_read_u32(i80_if_timings, "wr-active", &val)) in fimd_probe()
1119 val = 1; in fimd_probe()
1120 ctx->i80ifcon |= LCD_WR_ACTIVE(val); in fimd_probe()
1121 if (of_property_read_u32(i80_if_timings, "wr-hold", &val)) in fimd_probe()
1122 val = 0; in fimd_probe()
1123 ctx->i80ifcon |= LCD_WR_HOLD(val); in fimd_probe()