53 	 .p1 = {.min = 2, .max = 10},
65 	 .p1 = {.min = 2, .max = 10},
80 	 .p1 = {.min = 1, .max = 9},
92 	 .p1 = {.min = 1, .max = 10},
104 	 .p1 = {.min = 1, .max = 9},
116 	 .p1 = {.min = 1, .max = 10},
321 	p |= SET_FIELD(clock->p1, SB_P1_DIVIDER);  in cdv_dpll_set_clock_cdv()
405 	clock->p = clock->p1 * clock->p2;  in cdv_intel_clock()
421 			clock.p1 = 2;  in cdv_intel_find_dp_pll()
427 			clock.p1 = 1;  in cdv_intel_find_dp_pll()
437 			clock.p1 = 2;  in cdv_intel_find_dp_pll()
443 			clock.p1 = 1;  in cdv_intel_find_dp_pll()
843 	clock->p = clock->p1 * clock->p2;  in i8xx_clock()
886 		clock.p1 =  in cdv_intel_crtc_clock_get()
890 		if (clock.p1 == 0) {  in cdv_intel_crtc_clock_get()
891 			clock.p1 = 4;  in cdv_intel_crtc_clock_get()
904 			clock.p1 = 2;  in cdv_intel_crtc_clock_get()
906 			clock.p1 =  in cdv_intel_crtc_clock_get()