258 	uint32_t output_reg;  member
574 	uint32_t output_reg = intel_dp->output_reg;  in cdv_intel_dp_aux_ch()  local
576 	uint32_t ch_ctl = output_reg + 0x10;  in cdv_intel_dp_aux_ch()
1089 	REG_WRITE(intel_dp->output_reg, (intel_dp->DP | DP_PORT_EN));  in cdv_intel_dp_mode_set()
1175 	uint32_t dp_reg = REG_READ(intel_dp->output_reg);  in cdv_intel_dp_dpms()
1394 	REG_WRITE(intel_dp->output_reg, dp_reg_value);  in cdv_intel_dp_set_link_train()
1395 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_set_link_train()
1440 	if (intel_dp->output_reg == DP_B)  in cdv_intel_dp_set_vswing_premph()
1516 	REG_WRITE(intel_dp->output_reg, reg);  in cdv_intel_dp_start_link_train()
1517 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_start_link_train()
1672 	REG_WRITE(intel_dp->output_reg, reg);  in cdv_intel_dp_complete_link_train()
1673 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_complete_link_train()
1685 	if ((REG_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)  in cdv_intel_dp_link_down()
1693 		REG_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);  in cdv_intel_dp_link_down()
1695 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_link_down()
1699 	REG_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);  in cdv_intel_dp_link_down()
1700 	REG_READ(intel_dp->output_reg);  in cdv_intel_dp_link_down()
1997 cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg)  in cdv_intel_dp_init()  argument
2017 	if ((output_reg == DP_C) && cdv_intel_dpc_is_edp(dev))  in cdv_intel_dp_init()
2036 	intel_dp->output_reg = output_reg;  in cdv_intel_dp_init()
2048 	switch (output_reg) {  in cdv_intel_dp_init()