377 	uint16_t val;  in ivch_dump_regs()  local
379 	ivch_read(dvo, VR00, &val);  in ivch_dump_regs()
380 	DRM_DEBUG_KMS("VR00: 0x%04x\n", val);  in ivch_dump_regs()
381 	ivch_read(dvo, VR01, &val);  in ivch_dump_regs()
382 	DRM_DEBUG_KMS("VR01: 0x%04x\n", val);  in ivch_dump_regs()
383 	ivch_read(dvo, VR30, &val);  in ivch_dump_regs()
384 	DRM_DEBUG_KMS("VR30: 0x%04x\n", val);  in ivch_dump_regs()
385 	ivch_read(dvo, VR40, &val);  in ivch_dump_regs()
386 	DRM_DEBUG_KMS("VR40: 0x%04x\n", val);  in ivch_dump_regs()
389 	ivch_read(dvo, VR80, &val);  in ivch_dump_regs()
390 	DRM_DEBUG_KMS("VR80: 0x%04x\n", val);  in ivch_dump_regs()
391 	ivch_read(dvo, VR81, &val);  in ivch_dump_regs()
392 	DRM_DEBUG_KMS("VR81: 0x%04x\n", val);  in ivch_dump_regs()
393 	ivch_read(dvo, VR82, &val);  in ivch_dump_regs()
394 	DRM_DEBUG_KMS("VR82: 0x%04x\n", val);  in ivch_dump_regs()
395 	ivch_read(dvo, VR83, &val);  in ivch_dump_regs()
396 	DRM_DEBUG_KMS("VR83: 0x%04x\n", val);  in ivch_dump_regs()
397 	ivch_read(dvo, VR84, &val);  in ivch_dump_regs()
398 	DRM_DEBUG_KMS("VR84: 0x%04x\n", val);  in ivch_dump_regs()
399 	ivch_read(dvo, VR85, &val);  in ivch_dump_regs()
400 	DRM_DEBUG_KMS("VR85: 0x%04x\n", val);  in ivch_dump_regs()
401 	ivch_read(dvo, VR86, &val);  in ivch_dump_regs()
402 	DRM_DEBUG_KMS("VR86: 0x%04x\n", val);  in ivch_dump_regs()
403 	ivch_read(dvo, VR87, &val);  in ivch_dump_regs()
404 	DRM_DEBUG_KMS("VR87: 0x%04x\n", val);  in ivch_dump_regs()
405 	ivch_read(dvo, VR88, &val);  in ivch_dump_regs()
406 	DRM_DEBUG_KMS("VR88: 0x%04x\n", val);  in ivch_dump_regs()
409 	ivch_read(dvo, VR8E, &val);  in ivch_dump_regs()
410 	DRM_DEBUG_KMS("VR8E: 0x%04x\n", val);  in ivch_dump_regs()
413 	ivch_read(dvo, VR8F, &val);  in ivch_dump_regs()
414 	DRM_DEBUG_KMS("VR8F: 0x%04x\n", val);  in ivch_dump_regs()