Lines Matching refs:PIPE_CRC_ENABLE
3232 *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; in i8xx_pipe_crc_ctl_reg()
3312 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; in vlv_pipe_crc_ctl_reg()
3315 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; in vlv_pipe_crc_ctl_reg()
3319 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; in vlv_pipe_crc_ctl_reg()
3325 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; in vlv_pipe_crc_ctl_reg()
3383 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; in i9xx_pipe_crc_ctl_reg()
3388 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; in i9xx_pipe_crc_ctl_reg()
3393 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; in i9xx_pipe_crc_ctl_reg()
3399 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; in i9xx_pipe_crc_ctl_reg()
3405 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; in i9xx_pipe_crc_ctl_reg()
3494 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; in ilk_pipe_crc_ctl_reg()
3497 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; in ilk_pipe_crc_ctl_reg()
3500 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; in ilk_pipe_crc_ctl_reg()
3573 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; in ivb_pipe_crc_ctl_reg()
3576 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; in ivb_pipe_crc_ctl_reg()
3582 *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; in ivb_pipe_crc_ctl_reg()